{
    "schema_version": "via_ai_product_manager_jobs_v1",
    "data_type": "ai_product_manager_jobs",
    "job": {
        "job_title": "平头哥-资深AI芯片互联架构师-上海",
        "job_level": "高级",AI生成
        "work_category": "全职",AI生成
        "department": "阿里集团",
        "location": "上海",
        "work_mode": "未披露",AI生成
        "job_category": "技术-芯片"AI生成
    },
    "company": {
        "company_name": "平头哥",
        "company_industry": "半导体 / 芯片设计",
        "company_size": "未披露",
        "company_website": "alibaba.com",
        "company_description": "平头哥研发计算、存储及网络芯片，为人工智能基础设施提供支持。"
    },
    "compensation": {
        "salary_range": {
            "min": "",
            "max": "",
            "currency": "未披露",
            "cycle": "未披露"
        },
        "benefits": "未披露"
    },
    "requirements": {
        "working_years": "",
        "degree": "* Minimum Bachelor degree in Computer Science or Electronics Engineering",
        "language": "未披露",AI生成
        "visa_support": "未披露",
        "responsibilities": "In this role, you will work with hardware and software engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. \n* Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod.\n* Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. \n* Leads architecture design of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. \n* Documents the high-level architecture specification.\n* Participation in defining the micro-architecture of key subsystem. \n* Strong technical leadership to achieve successful delivery of final silicon product. \n* Works closely with design, software, system, and verification team.",
        "requirements_text": "* Minimum Bachelor degree in Computer Science or Electronics Engineering; M.S. or Ph.D. degree is preferred. \n* Minimum of 12 years (for M.S.) 8 years (for Ph.D.) of experience on computer architecture or network chip design with proven silicon result. \n* Strong experience in at least one of the following areas and have experience of technical leadership of successful chip development from architecture design to final production is a must:\n1.Server AI chip.\n2.Smart NIC/RDMA/RoCE/DPU.\n3.State-of-the-art Switch chip (25.6T and above).\n* Hand-on experience of high-speed interface, such as Die to Die, high speed long-reach SerDes, MAC/PCS, FEC is a plus. \n* Hand-on experience of interconnects in AI domain is a big plus. \n* Strong knowledge of AI infrastructure and AI network including Scale-up/Scale-out network, and knowledge of LLM inference and training is a big plus. \n* Good verbal and written skill for communication.",
        "skills": [AI生成
            "大语言模型"
        ],
        "preferred_qualifications": "M.S. or Ph.D. degree is preferred.",
        "job_highlights": "未披露"
    },
    "contact": {
        "recruiter_name": "未披露",
        "contact_methods": [
            {
                "type": "apply_link",
                "value": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=100007160014"
            }
        ]
    },
    "posting": {
        "posting_id": "100007160014",
        "post_date": "2026-07-30",
        "hire_time": "未披露",
        "update_date": "20260917",
        "job_url": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=100007160014"
    },
    "fulltext": "平头哥-资深AI芯片互联架构师-上海\n平头哥-资深AI芯片互联架构师-上海\n\n基础信息\n职位类别：技术-芯片\n工作地点：上海\n\n职位描述\nIn this role, you will work with hardware and software engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. \n* Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod.\n* Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. \n* Leads architecture design of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. \n* Documents the high-level architecture specification.\n* Participation in defining the micro-architecture of key subsystem. \n* Strong technical leadership to achieve successful delivery of final silicon product. \n* Works closely with design, software, system, and verification team.\n\n职位要求\n* Minimum Bachelor degree in Computer Science or Electronics Engineering; M.S. or Ph.D. degree is preferred. \n* Minimum of 12 years (for M.S.) 8 years (for Ph.D.) of experience on computer architecture or network chip design with proven silicon result. \n* Strong experience in at least one of the following areas and have experience of technical leadership of successful chip development from architecture design to final production is a must:\n1.Server AI chip.\n2.Smart NIC/RDMA/RoCE/DPU.\n3.State-of-the-art Switch chip (25.6T and above).\n* Hand-on experience of high-speed interface, such as Die to Die, high speed long-reach SerDes, MAC/PCS, FEC is a plus. \n* Hand-on experience of interconnects in AI domain is a big plus. \n* Strong knowledge of AI infrastructure and AI network including Scale-up/Scale-out network, and knowledge of LLM inference and training is a big plus. \n* Good verbal and written skill for communication.\nIn this role, you will work with hardware and software engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. \n* Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod.\n* Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. \n* Leads architecture design of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. \n* Documents the high-level architecture specification.\n* Participation in defining the micro-architecture of key subsystem. \n* Strong technical leadership to achieve successful delivery of final silicon product. \n* Works closely with design, software, system, and verification team.\n* Minimum Bachelor degree in Computer Science or Electronics Engineering; M.S. or Ph.D. degree is preferred. \n* Minimum of 12 years (for M.S.) 8 years (for Ph.D.) of experience on computer architecture or network chip design with proven silicon result. \n* Strong experience in at least one of the following areas and have experience of technical leadership of successful chip development from architecture design to final production is a must:\n1.Server AI chip.\n2.Smart NIC/RDMA/RoCE/DPU.\n3.State-of-the-art Switch chip (25.6T and above).\n* Hand-on experience of high-speed interface, such as Die to Die, high speed long-reach SerDes, MAC/PCS, FEC is a plus. \n* Hand-on experience of interconnects in AI domain is a big plus. \n* Strong knowledge of AI infrastructure and AI network including Scale-up/Scale-out network, and knowledge of LLM inference and training is a big plus. \n* Good verbal and written skill for communication.",
    "standard_classification": {
        "std_category_code": "T024",
        "std_aux_codes": [],
        "std_category_status": null,
        "std_taxonomy_version": "20261104"
    }
}