{
    "schema_version": "via_ai_product_manager_jobs_v1",
    "data_type": "ai_product_manager_jobs",
    "job": {
        "job_title": "平头哥-AI 芯片PCIE 设计专家-上海",
        "job_level": "专家",AI生成
        "work_category": "全职",AI生成
        "department": "阿里集团",
        "location": "上海",
        "work_mode": "未披露",AI生成
        "job_category": "技术-芯片"AI生成
    },
    "company": {
        "company_name": "平头哥",
        "company_industry": "半导体 / 芯片设计",
        "company_size": "未披露",
        "company_website": "alibaba.com",
        "company_description": "平头哥研发计算、存储及网络芯片，为人工智能基础设施提供支持。"
    },
    "compensation": {
        "salary_range": {
            "min": "",
            "max": "",
            "currency": "未披露",
            "cycle": "未披露"
        },
        "benefits": "未披露"
    },
    "requirements": {
        "working_years": 5,
        "degree": "硕士",
        "language": "未披露",AI生成
        "visa_support": "未披露",
        "responsibilities": "In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center.\n· According to SOC architecture, evaluate PCIE subsystem feature requirement include but not limited to PCIE protocol/PPA improvement/SRIOV virtualization etc.\n· As the PCIE subsystem IP owner, integration and glue logic RTL development for various of complex SOCs, high quality IP deliver with clean Lint/cdc/rdc and timing closure.\n· Strong problem solving and solution for PCIE design and IP integration, work together with DV owner and Emulation to cover PCIE related features. \n· Participate in post silicon bring up and PCIE related issue debug.",
        "requirements_text": "· Minimum of 5 years of experience on PCIE design for proven silicon.\n· Familiar with PCIE protocol, including physical layer/data link layer/transaction layer. \n· Familiar with PCIE Gen5/6 or CXL is plus.\n· Familiar with AMBA bus protocol like AXI/AHB/APB and CDC/RDC design flow.",
        "skills": [AI生成
            "问题分析"
        ],
        "preferred_qualifications": "未披露",
        "job_highlights": "未披露"
    },
    "contact": {
        "recruiter_name": "未披露",
        "contact_methods": [
            {
                "type": "apply_link",
                "value": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=100007500011"
            }
        ]
    },
    "posting": {
        "posting_id": "100007500011",
        "post_date": "2026-09-03",
        "hire_time": "未披露",
        "update_date": "20260917",
        "job_url": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=100007500011"
    },
    "fulltext": "平头哥-AI 芯片PCIE 设计专家-上海\n平头哥-AI 芯片PCIE 设计专家-上海\n\n基础信息\n职位类别：技术-芯片\n工作地点：上海\n\n职位描述\nIn this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center.\n· According to SOC architecture, evaluate PCIE subsystem feature requirement include but not limited to PCIE protocol/PPA improvement/SRIOV virtualization etc.\n· As the PCIE subsystem IP owner, integration and glue logic RTL development for various of complex SOCs, high quality IP deliver with clean Lint/cdc/rdc and timing closure.\n· Strong problem solving and solution for PCIE design and IP integration, work together with DV owner and Emulation to cover PCIE related features. \n· Participate in post silicon bring up and PCIE related issue debug.\n\n职位要求\n· Minimum of 5 years of experience on PCIE design for proven silicon.\n· Familiar with PCIE protocol, including physical layer/data link layer/transaction layer. \n· Familiar with PCIE Gen5/6 or CXL is plus.\n· Familiar with AMBA bus protocol like AXI/AHB/APB and CDC/RDC design flow.\nIn this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center.\n· According to SOC architecture, evaluate PCIE subsystem feature requirement include but not limited to PCIE protocol/PPA improvement/SRIOV virtualization etc.\n· As the PCIE subsystem IP owner, integration and glue logic RTL development for various of complex SOCs, high quality IP deliver with clean Lint/cdc/rdc and timing closure.\n· Strong problem solving and solution for PCIE design and IP integration, work together with DV owner and Emulation to cover PCIE related features. \n· Participate in post silicon bring up and PCIE related issue debug.\n· Minimum of 5 years of experience on PCIE design for proven silicon.\n· Familiar with PCIE protocol, including physical layer/data link layer/transaction layer. \n· Familiar with PCIE Gen5/6 or CXL is plus.\n· Familiar with AMBA bus protocol like AXI/AHB/APB and CDC/RDC design flow.",
    "standard_classification": {
        "std_category_code": "T024",
        "std_aux_codes": [],
        "std_category_status": null,
        "std_taxonomy_version": "20261104"
    }
}