{
    "schema_version": "via_ai_product_manager_jobs_v1",
    "data_type": "ai_product_manager_jobs",
    "job": {
        "job_title": "平头哥-DFT设计/DFT CAD开发高级工程师/专家-深圳",
        "job_level": "专家",AI生成
        "work_category": "全职",AI生成
        "department": "阿里集团",
        "location": "深圳",
        "work_mode": "未披露",AI生成
        "job_category": "技术-芯片"AI生成
    },
    "company": {
        "company_name": "平头哥",
        "company_industry": "半导体 / 芯片设计",
        "company_size": "未披露",
        "company_website": "alibaba.com",
        "company_description": "平头哥研发计算、存储及网络芯片，为人工智能基础设施提供支持。"
    },
    "compensation": {
        "salary_range": {
            "min": "",
            "max": "",
            "currency": "未披露",
            "cycle": "未披露"
        },
        "benefits": "未披露"
    },
    "requirements": {
        "working_years": 5,
        "degree": "7+ years for Bachelor or 5+ years for master degree experience in DFT design and verification",
        "language": "Good English hearing, speaking, reading and writing capabilities",AI生成
        "visa_support": "未披露",
        "responsibilities": "The candidate is expected to be responsible for following tasks:\n- Participate in complex Chip DFT/DFD feature and architecture definition\n- Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic\n- Generate DFT related timing constraints and work for timing closure\n- Develop and verify high coverage and cost effective test patterns for the production test\n- Design, implement and verify other DFX (debug, characterization, yield etc) feature\n- Evaluate and establish the advanced DFT/DFD tools and flow as DFT CAD",
        "requirements_text": "7+ years for Bachelor or 5+ years for master degree experience in DFT design and verification, test pattern development\nKEY KNOWLEDGE, SKILLS AND ABILITIES REQUIRED\n- Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques\n- Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc\n- Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding\n- Proficient in hardware description languages such as Verilog, System Verilog and VHDL\n- Good Knowledge of script language, such as Tcl, Python, Perl and DFT platform development skill is good plus for DFT CAD function\n- Good English hearing, speaking, reading and writing capabilities\n- Strong commitment to schedule and work quality, good team player",
        "skills": [AI生成
            "Python",
            "Verilog"
        ],
        "preferred_qualifications": "未披露",
        "job_highlights": "未披露"
    },
    "contact": {
        "recruiter_name": "未披露",
        "contact_methods": [
            {
                "type": "apply_link",
                "value": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=1025041"
            }
        ]
    },
    "posting": {
        "posting_id": "1025041",
        "post_date": "2026-09-15",
        "hire_time": "未披露",
        "update_date": "20260917",
        "job_url": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=1025041"
    },
    "fulltext": "平头哥-DFT设计/DFT CAD开发高级工程师/专家-深圳\n平头哥-DFT设计/DFT CAD开发高级工程师/专家-深圳\n\n基础信息\n职位类别：技术-芯片\n工作地点：深圳\n\n职位描述\nThe candidate is expected to be responsible for following tasks:\n- Participate in complex Chip DFT/DFD feature and architecture definition\n- Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic\n- Generate DFT related timing constraints and work for timing closure\n- Develop and verify high coverage and cost effective test patterns for the production test\n- Design, implement and verify other DFX (debug, characterization, yield etc) feature\n- Evaluate and establish the advanced DFT/DFD tools and flow as DFT CAD\n\n职位要求\n7+ years for Bachelor or 5+ years for master degree experience in DFT design and verification, test pattern development\nKEY KNOWLEDGE, SKILLS AND ABILITIES REQUIRED\n- Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques\n- Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc\n- Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding\n- Proficient in hardware description languages such as Verilog, System Verilog and VHDL\n- Good Knowledge of script language, such as Tcl, Python, Perl and DFT platform development skill is good plus for DFT CAD function\n- Good English hearing, speaking, reading and writing capabilities\n- Strong commitment to schedule and work quality, good team player\nThe candidate is expected to be responsible for following tasks:\n- Participate in complex Chip DFT/DFD feature and architecture definition\n- Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic\n- Generate DFT related timing constraints and work for timing closure\n- Develop and verify high coverage and cost effective test patterns for the production test\n- Design, implement and verify other DFX (debug, characterization, yield etc) feature\n- Evaluate and establish the advanced DFT/DFD tools and flow as DFT CAD\n7+ years for Bachelor or 5+ years for master degree experience in DFT design and verification, test pattern development\nKEY KNOWLEDGE, SKILLS AND ABILITIES REQUIRED\n- Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques\n- Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc\n- Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding\n- Proficient in hardware description languages such as Verilog, System Verilog and VHDL\n- Good Knowledge of script language, such as Tcl, Python, Perl and DFT platform development skill is good plus for DFT CAD function\n- Good English hearing, speaking, reading and writing capabilities\n- Strong commitment to schedule and work quality, good team player",
    "standard_classification": {
        "std_category_code": "T024",
        "std_aux_codes": [],
        "std_category_status": null,
        "std_taxonomy_version": "20261104"
    }
}