{
    "schema_version": "via_ai_product_manager_jobs_v1",
    "data_type": "ai_product_manager_jobs",
    "job": {
        "job_title": "平头哥-AI芯片SoC设计技术专家-上海",
        "job_level": "专家",AI生成
        "work_category": "全职",AI生成
        "department": "阿里集团",
        "location": "上海",
        "work_mode": "未披露",AI生成
        "job_category": "技术-芯片"AI生成
    },
    "company": {
        "company_name": "平头哥",
        "company_industry": "半导体 / 芯片设计",
        "company_size": "未披露",
        "company_website": "alibaba.com",
        "company_description": "平头哥研发计算、存储及网络芯片，为人工智能基础设施提供支持。"
    },
    "compensation": {
        "salary_range": {
            "min": "",
            "max": "",
            "currency": "未披露",
            "cycle": "未披露"
        },
        "benefits": "未披露"
    },
    "requirements": {
        "working_years": 5,
        "degree": "硕士",
        "language": "未披露",AI生成
        "visa_support": "未披露",
        "responsibilities": "In this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center.\n* as a design engineer, strong coding skill of system Verilog or Verilog to implement RTL design, develop SOC domain system/interface IP for various SOCs\n* familiar with ASIC flow to create complex SOCs with advanced methodologies more efficient, participated 3rd party IP integration\n* strong problem solving and solution for SOC design and IP integration, timing closure, silicon bring up and issue debug \n* Documents the high-level architecture specification that defines the chip with various sub-systems for the cutting-edge cloud applications.\n* Works closely with PD, power, system, and verification team to bring up the subsystem",
        "requirements_text": "* Minimum of 5 years of experience on complex SOC design for proven silicons.\n* Strong experience on following domain: CPU, GPU, PCIe, Memory, Network.\n* Experience on one or more of following domain: AXI 4.0(or higher), NOC, Coherency, Virtualization, Security, RAS, power management, SerDes, PHY.\n* Good verbal and written skill for communication\n* Hands-on experience on the performance simulation and analysis is a good plus\n* Server grade design, familiar with CLK/RESET tree implement, SPI/GPIO/UART/I3C peripheral IO is a plus.",
        "skills": [AI生成
            "Verilog"
        ],
        "preferred_qualifications": "未披露",
        "job_highlights": "未披露"
    },
    "contact": {
        "recruiter_name": "未披露",
        "contact_methods": [
            {
                "type": "apply_link",
                "value": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=7000036749"
            }
        ]
    },
    "posting": {
        "posting_id": "7000036749",
        "post_date": "2026-09-09",
        "hire_time": "未披露",
        "update_date": "20260917",
        "job_url": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=7000036749"
    },
    "fulltext": "平头哥-AI芯片SoC设计技术专家-上海\n平头哥-AI芯片SoC设计技术专家-上海\n\n基础信息\n职位类别：技术-芯片\n工作地点：上海\n\n职位描述\nIn this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center.\n* as a design engineer, strong coding skill of system Verilog or Verilog to implement RTL design, develop SOC domain system/interface IP for various SOCs\n* familiar with ASIC flow to create complex SOCs with advanced methodologies more efficient, participated 3rd party IP integration\n* strong problem solving and solution for SOC design and IP integration, timing closure, silicon bring up and issue debug \n* Documents the high-level architecture specification that defines the chip with various sub-systems for the cutting-edge cloud applications.\n* Works closely with PD, power, system, and verification team to bring up the subsystem\n\n职位要求\n* Minimum of 5 years of experience on complex SOC design for proven silicons.\n* Strong experience on following domain: CPU, GPU, PCIe, Memory, Network.\n* Experience on one or more of following domain: AXI 4.0(or higher), NOC, Coherency, Virtualization, Security, RAS, power management, SerDes, PHY.\n* Good verbal and written skill for communication\n* Hands-on experience on the performance simulation and analysis is a good plus\n* Server grade design, familiar with CLK/RESET tree implement, SPI/GPIO/UART/I3C peripheral IO is a plus.\nIn this role, you will work with software and hardware engineering groups to define the cutting edge of next-generation AI SOC chips for high-performance computing platform in Data Center.\n* as a design engineer, strong coding skill of system Verilog or Verilog to implement RTL design, develop SOC domain system/interface IP for various SOCs\n* familiar with ASIC flow to create complex SOCs with advanced methodologies more efficient, participated 3rd party IP integration\n* strong problem solving and solution for SOC design and IP integration, timing closure, silicon bring up and issue debug \n* Documents the high-level architecture specification that defines the chip with various sub-systems for the cutting-edge cloud applications.\n* Works closely with PD, power, system, and verification team to bring up the subsystem\n* Minimum of 5 years of experience on complex SOC design for proven silicons.\n* Strong experience on following domain: CPU, GPU, PCIe, Memory, Network.\n* Experience on one or more of following domain: AXI 4.0(or higher), NOC, Coherency, Virtualization, Security, RAS, power management, SerDes, PHY.\n* Good verbal and written skill for communication\n* Hands-on experience on the performance simulation and analysis is a good plus\n* Server grade design, familiar with CLK/RESET tree implement, SPI/GPIO/UART/I3C peripheral IO is a plus.",
    "standard_classification": {
        "std_category_code": "T024",
        "std_aux_codes": [],
        "std_category_status": null,
        "std_taxonomy_version": "20261104"
    }
}