主分类：芯片设计与验证
来源 JD 数据（旧分类保留，当前主分类见上方）
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"job": {
"job_title": "平头哥-芯片后端设计专家-成都",
"job_level": "专家",AI生成
"work_category": "全职",AI生成
"department": "阿里集团",
"location": "成都",
"work_mode": "未披露",AI生成
"job_category": "技术-芯片"AI生成
},
"company": {
"company_name": "平头哥",
"company_industry": "半导体 / 芯片设计",
"company_size": "未披露",
"company_website": "alibaba.com",
"company_description": "平头哥研发计算、存储及网络芯片，为人工智能基础设施提供支持。"
},
"compensation": {
"salary_range": {
"min": "",
"max": "",
"currency": "未披露",
"cycle": "未披露"
},
"benefits": "未披露"
},
"requirements": {
"working_years": 5,
"degree": "本科",
"language": "未披露",AI生成
"visa_support": "未披露",
"responsibilities": "As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization.\nYou responsibilities include, but not limited to:\n* Build backend flow on state-of-the-art processing node\n* Create SPECs for PD sign-off\n* Work closely with architecture and design team to optimize PPA\n* Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc.\n* Design and timing ECOs and sign-offs",
"requirements_text": "BS or MS of EE, 5+ years of experience with the whole RTL2GDS process\n* Understanding the state-of-the-art of processing node, custom lib and optimizations\n* State-of-the-art experience with CTS and power grid planning, power integrity is a plus \n* Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power\n* Understanding of DVFS, DFT, DFY, DFM is a plus\nSome hands on with following tools are needed:\n* Floor planning and P&R: Cadence Innovus and/or Synopsys ICC2\n* Synthesis: Synopsys DC/DCG\n* Formal Verification : Synopsys Formality and/or Cadence LEC\n* STA: Primetime-DMSA\n* PI : Apache Redhawk\n* Physical Design Verification: Synopsys ICV, Mentor Calibre\n* Scripting: TCL/Perl is required, Python is a plus",
"skills": [AI生成
"Python"
],
"preferred_qualifications": "未披露",
"job_highlights": "未披露"
},
"contact": {
"recruiter_name": "未披露",
"contact_methods": [
{
"type": "apply_link",
"value": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=725027"
}
]
},
"posting": {
"posting_id": "725027",
"post_date": "2026-09-01",
"hire_time": "未披露",
"update_date": "20260917",
"job_url": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=725027"
},
"fulltext": "平头哥-芯片后端设计专家-成都\n平头哥-芯片后端设计专家-成都\n\n基础信息\n职位类别：技术-芯片\n工作地点：成都\n\n职位描述\nAs a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization.\nYou responsibilities include, but not limited to:\n* Build backend flow on state-of-the-art processing node\n* Create SPECs for PD sign-off\n* Work closely with architecture and design team to optimize PPA\n* Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc.\n* Design and timing ECOs and sign-offs\n\n职位要求\nBS or MS of EE, 5+ years of experience with the whole RTL2GDS process\n* Understanding the state-of-the-art of processing node, custom lib and optimizations\n* State-of-the-art experience with CTS and power grid planning, power integrity is a plus \n* Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power\n* Understanding of DVFS, DFT, DFY, DFM is a plus\nSome hands on with following tools are needed:\n* Floor planning and P&R: Cadence Innovus and/or Synopsys ICC2\n* Synthesis: Synopsys DC/DCG\n* Formal Verification : Synopsys Formality and/or Cadence LEC\n* STA: Primetime-DMSA\n* PI : Apache Redhawk\n* Physical Design Verification: Synopsys ICV, Mentor Calibre\n* Scripting: TCL/Perl is required, Python is a plus\nAs a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization.\nYou responsibilities include, but not limited to:\n* Build backend flow on state-of-the-art processing node\n* Create SPECs for PD sign-off\n* Work closely with architecture and design team to optimize PPA\n* Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc.\n* Design and timing ECOs and sign-offs\nBS or MS of EE, 5+ years of experience with the whole RTL2GDS process\n* Understanding the state-of-the-art of processing node, custom lib and optimizations\n* State-of-the-art experience with CTS and power grid planning, power integrity is a plus \n* Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power\n* Understanding of DVFS, DFT, DFY, DFM is a plus\nSome hands on with following tools are needed:\n* Floor planning and P&R: Cadence Innovus and/or Synopsys ICC2\n* Synthesis: Synopsys DC/DCG\n* Formal Verification : Synopsys Formality and/or Cadence LEC\n* STA: Primetime-DMSA\n* PI : Apache Redhawk\n* Physical Design Verification: Synopsys ICV, Mentor Calibre\n* Scripting: TCL/Perl is required, Python is a plus",
"standard_classification": {
"std_category_code": "T024",
"std_aux_codes": [],
"std_category_status": null,
"std_taxonomy_version": "20261104"
}
}