主分类：芯片设计与验证
来源 JD 数据（旧分类保留，当前主分类见上方）
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"job": {
"job_title": "平头哥-AI芯片互联设计专家-上海",
"job_level": "专家",AI生成
"work_category": "全职",AI生成
"department": "阿里集团",
"location": "上海",
"work_mode": "未披露",AI生成
"job_category": "技术-芯片"AI生成
},
"company": {
"company_name": "平头哥",
"company_industry": "半导体 / 芯片设计",
"company_size": "未披露",
"company_website": "alibaba.com",
"company_description": "平头哥研发计算、存储及网络芯片，为人工智能基础设施提供支持。"
},
"compensation": {
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"currency": "未披露",
"cycle": "未披露"
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"degree": "M.S. or Ph.D. is preferred",
"language": "未披露",AI生成
"visa_support": "未披露",
"responsibilities": "In this role, you will work with software and hardware engineering groups to define the next-generation inter-chip network architecture for high-performance computing SOC in Data Center \nRequirement of the Job \n* Identifies the challenging problems, and evaluate the various solutions for next-generation data center Computing solutions.\n* Gets strong influences on the shape of future products by advanced architecture design as the excellent interface between software and hardware\n* Documents the high-level architecture specification that defines the inter-chip network subsystem for the cutting-edge cloud applications. \n* Works closely with design, system, and verification team to bring up the subsystem",
"requirements_text": "* Minimum Bachelar degree in Computer Science or Electronics Engineering; M.S. or Ph.D. is preferred \n* Minimum of 5 years of experience on computer architecture design for proven silicons. Ethernet/Switch/RDMA/RoCE/Ethernet sub-domain is preferred\n* Strong experience on Ethernet/RDMA/RoCE protocol and architecture design. \n* Experience on one or more of the following areas: Cache, NOC, Coherency, Virtulization, Security, RAS, power management\n* Good verbal and written skill for communication \n* Hands-on experience on the performance simulation and analysis is a good plus\n* Faimilar AMBA protocol, CPU, knowledgable about SerDes, Phy, participated the chip integration, Server grade design is a plus.",
"skills": [AI生成
"沟通能力"
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"preferred_qualifications": "M.S. or Ph.D. is preferred；* Minimum of 5 years of experience on computer architecture design for proven silicons. Ethernet/Switch/RDMA/RoCE/Ethernet sub-domain is preferred",
"job_highlights": "未披露"
},
"contact": {
"recruiter_name": "未披露",
"contact_methods": [
{
"type": "apply_link",
"value": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=799401"
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"posting": {
"posting_id": "799401",
"post_date": "2026-09-09",
"hire_time": "未披露",
"update_date": "20260917",
"job_url": "https://recruitment.t-head.cn/off-campus/position-detail?positionId=799401"
},
"fulltext": "平头哥-AI芯片互联设计专家-上海\n平头哥-AI芯片互联设计专家-上海\n\n基础信息\n职位类别：技术-芯片\n工作地点：上海\n\n职位描述\nIn this role, you will work with software and hardware engineering groups to define the next-generation inter-chip network architecture for high-performance computing SOC in Data Center \nRequirement of the Job \n* Identifies the challenging problems, and evaluate the various solutions for next-generation data center Computing solutions.\n* Gets strong influences on the shape of future products by advanced architecture design as the excellent interface between software and hardware\n* Documents the high-level architecture specification that defines the inter-chip network subsystem for the cutting-edge cloud applications. \n* Works closely with design, system, and verification team to bring up the subsystem\n\n职位要求\n* Minimum Bachelar degree in Computer Science or Electronics Engineering; M.S. or Ph.D. is preferred \n* Minimum of 5 years of experience on computer architecture design for proven silicons. Ethernet/Switch/RDMA/RoCE/Ethernet sub-domain is preferred\n* Strong experience on Ethernet/RDMA/RoCE protocol and architecture design. \n* Experience on one or more of the following areas: Cache, NOC, Coherency, Virtulization, Security, RAS, power management\n* Good verbal and written skill for communication \n* Hands-on experience on the performance simulation and analysis is a good plus\n* Faimilar AMBA protocol, CPU, knowledgable about SerDes, Phy, participated the chip integration, Server grade design is a plus.\nIn this role, you will work with software and hardware engineering groups to define the next-generation inter-chip network architecture for high-performance computing SOC in Data Center \nRequirement of the Job \n* Identifies the challenging problems, and evaluate the various solutions for next-generation data center Computing solutions.\n* Gets strong influences on the shape of future products by advanced architecture design as the excellent interface between software and hardware\n* Documents the high-level architecture specification that defines the inter-chip network subsystem for the cutting-edge cloud applications. \n* Works closely with design, system, and verification team to bring up the subsystem\n* Minimum Bachelar degree in Computer Science or Electronics Engineering; M.S. or Ph.D. is preferred \n* Minimum of 5 years of experience on computer architecture design for proven silicons. Ethernet/Switch/RDMA/RoCE/Ethernet sub-domain is preferred\n* Strong experience on Ethernet/RDMA/RoCE protocol and architecture design. \n* Experience on one or more of the following areas: Cache, NOC, Coherency, Virtulization, Security, RAS, power management\n* Good verbal and written skill for communication \n* Hands-on experience on the performance simulation and analysis is a good plus\n* Faimilar AMBA protocol, CPU, knowledgable about SerDes, Phy, participated the chip integration, Server grade design is a plus.",
"standard_classification": {
"std_category_code": "T024",
"std_aux_codes": [],
"std_category_status": null,
"std_taxonomy_version": "20261104"
}
}