{
    "summary": {
        "overall_match": "候选人具备扎实的FPGA开发基础与芯片流片经验，核心技能与岗位高度匹配，但缺乏图像处理和LVDS接口的直接经验，且多项关键信息（薪资、到岗、加班意愿）缺失，导致整体评估证据不足。",
        "key_strengths": [
            "具备3年FPGA开发经验，主导过工业网络芯片从架构到流片的端到端交付",
            "熟练掌握Verilog及多厂商FPGA平台，具备PCIe高速采集等复杂项目经验",
            "当前所在城市与岗位地点一致，简历结构清晰、表达专业"
        ],
        "key_concerns": [
            "简历未体现图像处理及LVDS接口经验，与JD筛选标准存在差距",
            "未提供期望薪资、到岗时间及对大小周\/早9晚9工作制的接受意愿",
            "仅有一段正式工作经历，稳定性维度证据不足"
        ],
        "recommendation_summary": "因信息覆盖率（35%）和整体置信度（35%）均低于阈值，触发证据不足拦截，建议补充关键信息后再做决策。"
    },
    "jd_analysis": {
        "must_requirements": [
            "统招本科以上学历",
            "3年以上图像处理\/信号处理算法FPGA开发经验",
            "熟练掌握Verilog语言",
            "高速信号调试经验，熟悉MIPI、PCIE、USB、LVDS等接口",
            "大规模电路逻辑设计和调试经验，解决复杂时序问题",
            "熟练阅读英文文档",
            "接受研发攻关期加班和工作压力",
            "工作地点：深圳",
            "工作安排：大小周(早9晚9)"
        ],
        "preferred_requirements": [
            {
                "requirement": "超高分辨率智能工业相机\/计算成像传感产品的图像视觉算法硬件逻辑实现经验",
                "importance": "high"
            },
            {
                "requirement": "MIPI、USB接口开发经验",
                "importance": "medium"
            }
        ],
        "job_environment": {
            "city": "深圳",
            "work_mode": "线下办公（源政创业大厦）",
            "pace": "大小周，早9晚9，研发攻关期加班",
            "company_stage": "高速成长期，清华团队",
            "arrival_requirement": "2026-07-31"
        },
        "salary_range": {
            "min_k": 22,
            "max_k": 30,
            "median_k": 26,
            "source": "explicit"
        }
    },
    "hard_requirements_check": [
        {
            "requirement": "统招本科以上学历",
            "status": "met",
            "evidence": "河南科技大学，测控技术与仪器，工学学士，2023年毕业。"
        },
        {
            "requirement": "3年以上FPGA开发经验",
            "status": "met",
            "evidence": "2023.7至今在固高科技担任FPGA工程师，刚好满3年。"
        },
        {
            "requirement": "熟练掌握Verilog",
            "status": "met",
            "evidence": "专业技能中明确列出Verilog、SystemVerilog，并在多个项目中应用。"
        },
        {
            "requirement": "高速信号调试及LVDS\/图像经验（筛选标准）",
            "status": "partially_met",
            "evidence": "具备PCIe、高速ADC采样等高速信号经验，但简历未明确提及LVDS接口及图像处理\/视觉算法经验。"
        },
        {
            "requirement": "熟练阅读英文文档",
            "status": "met",
            "evidence": "CET-4（451分），自述可熟练阅读英文Datasheet与技术文档。"
        },
        {
            "requirement": "接受加班和大小周",
            "status": "unknown",
            "evidence": "简历未提及对大小周及早9晚9工作制的接受意愿。"
        }
    ],
    "dimensions": [
        {
            "name": "tech_power",
            "raw_score": 95,
            "confidence_level": "high",
            "confidence_coefficient": 1,
            "adjusted_score": 95,
            "base_weight": 0.3,
            "adjusted_weight": 0.857,
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50,
                    "evidence": "基准分"
                },
                {
                    "item": "统招本科学历",
                    "score_change": 10,
                    "evidence": "河南科技大学工学学士"
                },
                {
                    "item": "3年FPGA开发经验",
                    "score_change": 10,
                    "evidence": "2023.7至今任职FPGA工程师"
                },
                {
                    "item": "核心技能满足度",
                    "score_change": 10,
                    "evidence": "Verilog\/PCIe\/时序\/英文满足，但图像\/LVDS部分满足"
                },
                {
                    "item": "复杂项目证据",
                    "score_change": 15,
                    "evidence": "主导工业网络芯片流片，具备PCIe高速采集等项目经验"
                }
            ],
            "reason": "候选人具备扎实的FPGA底层开发与芯片流片经验，核心技能高度匹配，但在JD筛选标准强调的图像处理和LVDS接口方面缺乏直接证据，故核心要求判定为部分满足。",
            "jd_requirement": "3年以上图像\/信号处理FPGA经验，精通Verilog，熟悉LVDS\/PCIe等高速接口，具备大规模逻辑设计与时序解决能力。",
            "resume_fulfillment": "具备3年FPGA经验，精通Verilog，有PCIe和高速ADC经验，主导过芯片流片。但缺乏图像处理和LVDS的直接项目经验。"
        },
        {
            "name": "stability",
            "raw_score": 50,
            "confidence_level": "low",
            "confidence_coefficient": 0,
            "adjusted_score": null,
            "base_weight": 0.25,
            "adjusted_weight": null,
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50,
                    "evidence": "基准分"
                }
            ],
            "reason": "候选人仅有一段有效正式工作经历，根据规则不纳入综合分计算。",
            "jd_requirement": "未明确说明，默认评估任职稳定性。",
            "resume_fulfillment": "2023.7至今在固高科技任职，仅一段正式工作经历。"
        },
        {
            "name": "salary_match",
            "raw_score": 50,
            "confidence_level": "low",
            "confidence_coefficient": 0,
            "adjusted_score": null,
            "base_weight": 0.2,
            "adjusted_weight": null,
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50,
                    "evidence": "基准分"
                }
            ],
            "reason": "候选人未提供期望薪资，无法评估匹配度，不纳入综合分。",
            "jd_requirement": "22-30K",
            "resume_fulfillment": "未提供期望薪资。"
        },
        {
            "name": "pace_match",
            "raw_score": 60,
            "confidence_level": "low",
            "confidence_coefficient": 0,
            "adjusted_score": null,
            "base_weight": 0.2,
            "adjusted_weight": null,
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50,
                    "evidence": "基准分"
                },
                {
                    "item": "当前城市匹配",
                    "score_change": 10,
                    "evidence": "候选人当前在深圳"
                }
            ],
            "reason": "候选人当前城市匹配，但未说明是否接受大小周及到岗时间，置信度降为low，不纳入综合分。",
            "jd_requirement": "深圳线下办公，大小周早9晚9，2026-07-31到岗。",
            "resume_fulfillment": "当前在深圳，但未说明是否接受大小周\/早9晚9，未提供到岗时间。"
        },
        {
            "name": "communication",
            "raw_score": 95,
            "confidence_level": "high",
            "confidence_coefficient": 1,
            "adjusted_score": 95,
            "base_weight": 0.05,
            "adjusted_weight": 0.143,
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50,
                    "evidence": "基准分"
                },
                {
                    "item": "结构清晰",
                    "score_change": 10,
                    "evidence": "模块划分合理，阅读顺序清晰"
                },
                {
                    "item": "字段完整",
                    "score_change": 10,
                    "evidence": "教育、工作、项目、技能等关键字段完整"
                },
                {
                    "item": "证据表达",
                    "score_change": 15,
                    "evidence": "项目描述包含背景、动作与明确结果（如流片、采集速率）"
                },
                {
                    "item": "一致性",
                    "score_change": 10,
                    "evidence": "时间线与技能声明相互一致"
                }
            ],
            "reason": "简历结构专业，信息完整度高，项目描述具备清晰的STAR法则特征，表达质量优秀。",
            "jd_requirement": "无直接要求，评估简历信息表达质量。",
            "resume_fulfillment": "简历结构清晰，字段完整，项目成果描述具体，时间线一致。"
        }
    ],
    "information_coverage": 0.35,
    "overall_confidence": 0.35,
    "match_score": 95,
    "bonus_items": [
        {
            "dimension": "tech_power",
            "score": 95,
            "confidence": "high",
            "impact": 4.5,
            "evidence": "具备芯片流片及PCIe高速采集等复杂项目经验，核心技能扎实"
        },
        {
            "dimension": "communication",
            "score": 95,
            "confidence": "high",
            "impact": 0.75,
            "evidence": "简历结构专业，项目描述具备清晰的背景、动作与结果"
        }
    ],
    "risks": {
        "hard_constraint_risks": [],
        "confirmed_high_risks": [],
        "potential_risks": [
            {
                "dimension": "tech_power",
                "risk_type": "potential_risk",
                "description": "JD筛选标准明确要求图像和LVDS经验，候选人具备高速信号经验但缺乏图像处理和LVDS的直接证据，核心要求仅为部分满足。",
                "impact": 0
            }
        ]
    },
    "missing_information": [
        "候选人期望薪资",
        "候选人到岗时间",
        "是否接受大小周及早9晚9工作制",
        "图像处理及LVDS接口相关经验"
    ],
    "recommendation": "pending",
    "recommendation_reason": "insufficient_evidence"
}

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