{
    "summary": {
        "overall_match": "候选人技术能力与岗位高度匹配，具备扎实的FPGA与图像处理项目经验，但稳定性、薪资期望及工作节奏接受度等关键信息缺失。",
        "key_strengths": [
            "核心技术高度匹配，精通FPGA开发、图像处理及高速接口（VBO\/PCIE\/JESD204b）",
            "项目成果丰富且量化指标明确（如色差ΔE<1.0），拥有发明专利及竞赛奖项"
        ],
        "key_concerns": [
            "仅有一段正式工作经历且不足24个月，长期稳定性有待观察",
            "未提供期望薪资，且未明确是否接受大小周及早9晚9的工作节奏"
        ],
        "recommendation_summary": "技术匹配度极高，综合分优秀，但由于稳定性、薪资和节奏等关键信息缺失导致整体置信度不足，建议推进面试以进一步核实相关信息。"
    },
    "dimensions": [
        {
            "name": "tech_power",
            "raw_score": 98,
            "confidence_level": "high",
            "jd_requirement": "统招本科以上，3年以上研发（推测为FPGA\/图像处理\/硬件）经验，具备视觉传感器或相关研发能力。",
            "resume_fulfillment": "硕士学历，电子信息专业。具备扎实的FPGA开发、图像处理及高速接口经验，项目成果丰富且有明确量化指标，拥有发明专利。硕士折算2年加正式工作约1.9年，认可工作年限约3.9年，满足3年以上要求。"
        },
        {
            "name": "stability",
            "raw_score": 50,
            "confidence_level": "low",
            "jd_requirement": "未明确说明，默认评估正式工作任职时长与稳定性。",
            "resume_fulfillment": "仅有一段正式工作经历（2024.08至今），任职不足24个月，信息不足以评估长期稳定性。"
        },
        {
            "name": "salary_match",
            "raw_score": 50,
            "confidence_level": "low",
            "jd_requirement": "22-30K",
            "resume_fulfillment": "候选人未在简历中提供期望薪资，无法评估匹配度。"
        },
        {
            "name": "pace_match",
            "raw_score": 60,
            "confidence_level": "low",
            "jd_requirement": "深圳-源政创业大厦，大小周(早9晚9)。",
            "resume_fulfillment": "现居深圳，地点匹配。但未说明是否接受大小周及早9晚9的工作节奏。"
        },
        {
            "name": "communication",
            "raw_score": 80,
            "confidence_level": "high",
            "jd_requirement": "无直接要求，评估简历信息表达质量。",
            "resume_fulfillment": "简历结构清晰，模块完整，项目描述包含背景、动作和量化结果。存在少量OCR识别错字，但不影响整体阅读与理解。"
        }
    ],
    "match_score": 96.4,
    "overall_confidence": 0.55,
    "recommendation": "pending"
}

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