简历初筛详情

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提取时间 extracted_at

2026-09-18 14:52:06

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etag etag

5BE2C0C599F1E384A4C5BC0E95ADE2A6

model model

qwen3.7-plus

文本长度 text_length

7715

jd_text jd_text

产研周远泽 2026-07-05T16:00:00.000Z FPGA工程师-深圳 2 全职普通 2026-07-30T16:00:00.000Z 关于朗伯威LAMBERV 高端视觉传感器供应商 | 国家级高新技术企业 | 清华团队 | 高速成长期企业朗伯威中国官网：www.lamberv.com 任职要求： 1、统招本科以上学历，3年以上图像处理/信号处理算法FPGA开发经验； 2、熟练的掌握掌握Verilog语言； 3、有高速信号调试经验，熟悉MIPI，PCIE，USB等接口；熟悉LVDS； 4、具有大规模电路逻辑设计经验和调试经验，能够解决复杂的时序问题； 5、具备数量阅读英文文档的能力； 6、能接受研发攻关期加班和一定的工作压力。岗位职责： 1、负责超高分辨率智能工业相机、计算成像传感产品的图像、视觉算法的硬件逻辑实现方案论证； 2、负责FPGA逻辑的设计、开发、调试以及维护等工作； 3、配合软件、硬件工程师进行产品设计开发过程中的软硬件联调和验证； 4、负责FPGA相关文档的撰写和整理。公司福利 1、办公室咖啡、小零食每日无限量供应； 2、核心团队来自清华大学，公司业务高速健康增长，产品研发采用前沿技术路线，提供有竞争力的职业晋升机会。 3、团队扁平化管理，成员年轻化，只要敢拼敢干，空间不设限；图像。LVDS 22-30K HC2026070605 67adaef1fe156cbf02573142 00050 [{'name': '周远泽', 'username': 'c945b5g9', 'status': 1, 'type': 0, 'departments': [3], 'integrate_id': 'c945b5g9'}, {'name': '唐汇沙', 'username': 'adb78383', 'status': 1, 'type': 0, 'departments': [3], 'integrate_id': 'adb78383'}] [{'name': '杨心杰', 'username': 'e3378688', 'status': 1, 'type': 0, 'departments': [29], 'integrate_id': 'e3378688'}] [{'name': '杨心杰', 'username': 'e3378688', 'status': 1, 'type': 0, 'departments': [29], 'integrate_id': 'e3378688'}] [{'name': '户孝围', 'username': '3eabb56d', 'status': 1, 'type': 0, 'departments': [22, 4], 'integrate_id': '3eabb56d'}] 社招深圳-源政创业大厦 3-5年大小周(早9晚9) 通过 2026-07-05T16:00:00.000Z 已启动 2026-07-05T16:00:00.000Z 119 40 24 8 3 1 7 1 2 未完成 0.5 FPGA 研发 80.66086957

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r3_json r3_json

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extracted_json extracted_json

JSON

{
    "summary": {
        "overall_match": "候选人具备丰富的FPGA及图像\/信号处理开发经验，核心技能与岗位高度匹配，但简历存在部分乱码且未明确表达对大小周及加班的接受意愿。",
        "key_strengths": [
            "FPGA及图像\/信号处理经验丰富，超出JD年限要求",
            "熟练掌握Verilog及高速接口(PCIE\/LVDS)调试",
            "具备Zynq\/SoC软硬协同及复杂时序设计能力"
        ],
        "key_concerns": [
            "未明确期望薪资及到岗时间",
            "未明确表态是否接受大小周及高强度加班",
            "简历文本包含乱码及无关系统元数据"
        ],
        "recommendation_summary": "技术能力高度匹配且稳定性良好，综合分达到approve标准，薪资及节奏偏好需后续沟通确认。"
    },
    "dimensions": [
        {
            "name": "tech_power",
            "raw_score": 90,
            "confidence_level": "high",
            "jd_requirement": "3年以上图像\/信号FPGA经验，熟练Verilog，高速信号调试(PCIE\/LVDS等)，解决复杂时序问题，熟练阅读英文文档。",
            "resume_fulfillment": "具备约4.6年FPGA开发经验（微谱智能、立仪科技），涉及高速像机、光谱共焦传感器等图像\/信号处理；熟练掌握Verilog及跨时钟域设计；有PCIE、LVDS、DDR3等高速接口调试经验；英语能力良好。",
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50
                },
                {
                    "item": "核心要求-图像\/信号FPGA经验充分满足",
                    "score_change": 20
                },
                {
                    "item": "核心要求-Verilog及复杂时序设计满足",
                    "score_change": 10
                },
                {
                    "item": "核心要求-高速接口调试部分满足",
                    "score_change": 5
                },
                {
                    "item": "核心要求-英文文档阅读满足",
                    "score_change": 3
                },
                {
                    "item": "经验深度-超出要求1-2年",
                    "score_change": 3
                },
                {
                    "item": "加分项-具备工业相机\/传感产品相关经验",
                    "score_change": 2
                }
            ],
            "adjusted_score": 90,
            "adjusted_weight": 0.526
        },
        {
            "name": "stability",
            "raw_score": 75,
            "confidence_level": "medium",
            "jd_requirement": "未明确说明，依据历史任职年限评估。",
            "resume_fulfillment": "最近一段工作（微谱智能）任职超过24个月，历史多段工作任职均较长，整体稳定性良好。",
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50
                },
                {
                    "item": "最近一段正式工作超过24个月",
                    "score_change": 25
                }
            ],
            "adjusted_score": 70,
            "adjusted_weight": 0.211
        },
        {
            "name": "salary_match",
            "raw_score": 50,
            "confidence_level": "low",
            "jd_requirement": "22-30K",
            "resume_fulfillment": "候选人未提供期望薪资，信息缺失。",
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50
                }
            ],
            "adjusted_score": null,
            "adjusted_weight": null
        },
        {
            "name": "pace_match",
            "raw_score": 60,
            "confidence_level": "medium",
            "jd_requirement": "深圳，大小周(早9晚9)，接受研发攻关期加班和压力。",
            "resume_fulfillment": "期望城市为深圳，当前也在深圳，地点匹配；但未明确说明是否接受大小周、早9晚9及加班，也未提供到岗时间。",
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50
                },
                {
                    "item": "当前地点与岗位城市匹配",
                    "score_change": 10
                }
            ],
            "adjusted_score": 58,
            "adjusted_weight": 0.211
        },
        {
            "name": "communication",
            "raw_score": 55,
            "confidence_level": "high",
            "jd_requirement": "无直接要求，评估简历信息表达质量。",
            "resume_fulfillment": "模块基本清晰，但包含大量乱码、水印及无关系统元数据，且部分经历描述存在重复和错别字。",
            "score_breakdown": [
                {
                    "item": "中性基准",
                    "score_change": 50
                },
                {
                    "item": "模块清晰、阅读顺序合理",
                    "score_change": 10
                },
                {
                    "item": "任职时间、职位等字段完整",
                    "score_change": 10
                },
                {
                    "item": "包含乱码、水印及无关系统元数据",
                    "score_change": -10
                },
                {
                    "item": "部分经历描述重复及存在错别字",
                    "score_change": -5
                }
            ],
            "adjusted_score": 55,
            "adjusted_weight": 0.053
        }
    ],
    "match_score": 77.2,
    "overall_confidence": 0.87,
    "information_coverage": 0.95,
    "missing_information": [
        "候选人未提供期望薪资",
        "候选人未提供到岗时间",
        "候选人未明确说明是否接受大小周、早9晚9及研发攻关期加班"
    ],
    "bonus_items": [
        {
            "dimension": "tech_power",
            "reason": "技术匹配原始分90，具备丰富的图像\/信号FPGA及高速接口调试经验，超出岗位基础要求。",
            "bonus_impact": 5
        }
    ],
    "risks": {
        "hard_constraint_risks": [],
        "confirmed_high_risks": [],
        "potential_risks": [
            {
                "dimension": "pace_match",
                "reason": "节奏匹配原始分为60，候选人未明确说明是否接受大小周、早9晚9及研发攻关期加班，需后续沟通确认其接受意愿。",
                "risk_impact": 0
            }
        ]
    },
    "recommendation": "approve",
    "recommendation_reason": "技术匹配度极高且稳定性良好，综合匹配分达到77.2分，符合approve标准。薪资及工作节奏偏好信息缺失，建议在后续面试中重点沟通确认。"
}

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recommended_action recommended_action

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创建时间 created_at

2026-09-18 22:53:43

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