简历解析详情

ID id

1036

请求 ID request_id

1-6aae73f5-15b6d2-2fd653265841

解析时间 parsed_at

2026-09-19 11:37:28

source_bucket source_bucket

langbowei-static

源对象 source_object

resumes/1-6aae73f5-15b6d2-2fd653265841__widget_1704704635359_0.png

对象大小 object_size

109779

文件类型 file_type

png

姓名 name

王亮

手机号 phone

event_name event_name

ObjectCreated:PutObject

event_time event_time

2026-09-19T11:37:26.000Z

region region

cn-hangzhou

etag etag

4294BD6579D037FC6528CDE0C470F2BE

文本长度 text_length

539

parsed_result parsed_result

JSON

{
    "basic_info": {
        "name": "王亮",
        "gender": "",
        "phone": "",
        "email": "",
        "age": "35",
        "birth_date": "",
        "location": "",
        "work_years": "10.0"
    },
    "education": [
        {
            "school": "佳木斯大学",
            "major": "通信工程",
            "degree": "本科",
            "graduation_year": "2015"
        }
    ],
    "job_intention": {
        "expected_position": "FPGA开发",
        "expected_salary": "面议",
        "expected_city": "杭州",
        "availability": "月内到岗"
    },
    "skills": [
        "FPGA开发",
        "高速信号处理",
        "实时图像采集与预处理",
        "高速SerDes收发",
        "以太网数据处理",
        "时钟恢复",
        "链路同步",
        "误码优化",
        "外设接口驱动",
        "图像传感器LVDS\/SerDes数据接收",
        "解码",
        "行缓存",
        "ISP算法",
        "Xilinx平台",
        "Altera平台",
        "lattice平台",
        "安路平台",
        "Modelsim",
        "vcs",
        "跨时钟域处理",
        "时序优化",
        "高速接口调试",
        "FPGA系统架构设计",
        "Protel",
        "RTL设计",
        "Verilog",
        "Quartus II"
    ],
    "work_experience": [
        {
            "company": "浙江华睿科技股份有限公司",
            "position": "FPGA开发",
            "duration": "2023\/03 - Present",
            "description": "FPGA开发功能；Protel RTL设计 Verilog Quartus II。方向集中在高速信号处理、实时图像采集与预处理。做过高速SerDes收发、以太网数据处理、时钟恢复、链路同步、误码优化、外设接口驱动FPGA端图像传感器LVDS\/SerDes数据接收、解码、行缓存、ISP算法。熟练使用Xilinx、Altera、lattice、安路等平台及Modelsim、vcs等仿真工具，精通跨时钟域处理、时序优化、高速接口调试，能够独立负责FPGA系统架构设计与关键问题攻关。"
        }
    ],
    "project_experience": [],
    "certifications": [],
    "self_evaluation": "10年FPGA开发经验，方向集中在高速信号处理、实时图像采集与预处理。做过高速SerDes收发、以太网数据处理、时钟恢复、链路同步、误码优化、外设接口驱动FPGA端图像传感器LVDS\/SerDes数据接收、解码、行缓存、ISP算法。技术上我熟练使用Xilinx平台、Altera平台，lattice平台、安路平台等开发工具以及Modelsim，vcs等仿真工具，精通跨时钟域处理、时序优化、高速接口调试，能够独立负责FPGA系统架构设计与关键问题攻关。"
}

output_key output_key

parsed/resumes/1-6aae73f5-15b6d2-2fd653265841__widget_1704704635359_0.png.parsed.json

状态 status

success

error_message error_message

无数据

raw_event raw_event

JSON

{
    "events": [
        {
            "eventName": "ObjectCreated:PutObject",
            "eventSource": "acs:oss",
            "eventTime": "2026-09-19T11:37:26.000Z",
            "eventVersion": "1.0",
            "oss": {
                "bucket": {
                    "arn": "acs:oss:cn-hangzhou:1748673497100614:langbowei-static",
                    "name": "langbowei-static",
                    "ownerIdentity": "1748673497100614",
                    "virtualBucket": ""
                },
                "object": {
                    "deltaSize": 109779,
                    "eTag": "4294BD6579D037FC6528CDE0C470F2BE",
                    "key": "resumes\/1-6aae73f5-15b6d2-2fd653265841__widget_1704704635359_0.png",
                    "objectMeta": {
                        "mimeType": "image\/png"
                    },
                    "size": 109779
                },
                "ossSchemaVersion": "1.0",
                "ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
            },
            "region": "cn-hangzhou",
            "requestParameters": {
                "sourceIPAddress": "172.16.0.144"
            },
            "responseElements": {
                "requestId": "6AAE73F672045C3535F62921"
            },
            "userIdentity": {
                "principalId": "300034963247836315"
            }
        }
    ]
}

创建时间 created_at

2026-09-19 19:38:43

记录详情