简历解析
#1074
记录详情
1-6ab0a219-154065-d1b44c644af5
success
2026-09-21 11:20:05
ID
id
1074
请求 ID
request_id
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解析时间
parsed_at
2026-09-21 03:18:52
source_bucket
source_bucket
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源对象
source_object
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对象大小
object_size
311218
文件类型
file_type
pdf
姓名
name
曾海波
手机号
phone
15521077237
event_name
event_name
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event_time
event_time
2026-09-21T03:18:50.000Z
region
region
cn-hangzhou
etag
etag
491DE6BDA0240240F16E8EE31B47C2A2
文本长度
text_length
2611
parsed_result
parsed_result
JSON
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"basic_info": {
"name": "曾海波",
"gender": null,
"phone": "15521077237",
"email": "1696940108@qq.com",
"age": null,
"birth_date": "1993\/05\/23",
"location": null,
"work_years": "7.7"
},
"education": [
{
"school": "广东工业大学",
"major": "微电子科学与工程",
"degree": "本科",
"graduation_year": "2018\/07"
}
],
"job_intention": {
"expected_position": null,
"expected_salary": null,
"expected_city": null,
"availability": null
},
"skills": [
"AMBA总线(APB\/AHB\/AXI)",
"UVM验证方法学",
"SystemVerilog",
"Verilog",
"FPGA\/CPLD开发与维护",
"UART\/I2C通信协议",
"EDA工具(verdi\/vivado\/quartus\/modelsim\/Cadence\/TannerPro)",
"Shell脚本",
"功能仿真与ChipScope调试",
"EMIF总线调试与时序分析"
],
"work_experience": [
{
"company": "深圳市勤远科技有限公司",
"position": "FAE",
"duration": "2018\/07 - 2021\/02",
"description": "从事FAE工作"
},
{
"company": "深圳市南航电子工业有限公司",
"position": "FPGA工程师",
"duration": "2021\/03 - 2026\/03",
"description": "担任FPGA工程师"
}
],
"project_experience": [
{
"name": "二主三从AXI4 Full Interconnect UVM验证",
"role": null,
"duration": null,
"description": "1.负责二主三从AXI4FullInterconnect的验证环境搭建,完成RTL对接、interface、agent、env、testcase与run.do工程集成。\n2.基于UVM搭建可复用验证平台,包含masteragent、virtualsequence、scoreboard、reference model与functionalcoverage。\n3.围绕burst、outstanding、out-of-order、backpressure、错误响应等场景设计15条核心testcase,并完成数据一致性检查。\n4.在QuestaSim上完成仿真调试与波形分析,能够结合log、coverage与scoreboard定位问题并总结验证结论。"
},
{
"name": "备份仪表的大气数据采集和数据处理",
"role": null,
"duration": null,
"description": "1.用计数器采集大气传感器频率,用等精度频率测量原理优化频率采集;\n2.编写外围通信芯片控制器,如16C554和arinc429等通信芯片,减轻DSP\/MCU工作量,通过双端RAM通信和FIFO控制传输的数据量;\n3.熟悉UART、I2C通讯,解析数据包;\n4.功能仿真、chipscope的信号抓取,故障分析与讨论,数据缺失、数据重复;\n5.调试emif总线,增加读写保护寄存器,保证数据传输准确不冲突,监控DSP是否异常给予复位;读写状态切换时序分析,保证DIR的切换满足时序要求。"
},
{
"name": "基于Xilinx Artix-7与MIG IP的128bit UI接口DDR3读写控制器设计",
"role": null,
"duration": null,
"description": "1.理解MIG UI命令通道与写数据通道解耦机制,采用单计数器统一握手推进,避免命令\/数据不匹配死锁;\n2.正确处理app_wdf_end=app_wdf_wren,固定app_sr_req\/app_ref_req\/app_zq_req=0,由MIG内部完成刷新与校准;\n3.基于init_calib_complete做访问保护,利用app_rd_data_valid自数拍完成读校验,产生end_flag作为类中断完成标志;\n4.ILA在线调试定位地址对齐与时序违例。"
},
{
"name": "高速LVDS串行接收与8b\/10b软解码系统设计",
"role": null,
"duration": null,
"description": "1.基于低成本Cyclone10LP器件,设计并实现了一套无硬SerDes的LVDS高速串行接收链路,支持200–400Mbps线速率、10bit串行化因子的自定义帧协议。\n2.采用ALTDDIO_IN双沿采样替代纯RTL过采样,利用PLL产生200MHz DDR时钟及90°相位偏移,在IOB硬资源内完成眼图中心数据判决。\n3.设计软Bitslip字对齐状态机,在2bit DDR并行流上滑动窗口搜索10bit同步字,实现稳定的符号边界恢复。\n4.构建2bit→10bit串并转换逻辑,完成帧拼接。\n5.针对跨时钟域,设计脉冲–电平握手CDC结构,避免数据撕裂与脉冲漏采。\n6.实现8b\/10b软解码模块,支持K28.5逗号检测、D\/K码区分及disparity错误指示。"
}
],
"certifications": [
"英语四级"
],
"self_evaluation": null
}
output_key
output_key
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状态
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success
error_message
error_message
无数据
raw_event
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创建时间
created_at
2026-09-21 11:20:05