简历解析
#1194
记录详情
1-6acca8ec-15693a-907ee9c86cab
success
2026-10-12 17:33:05
ID
id
1194
请求 ID
request_id
1-6acca8ec-15693a-907ee9c86cab
解析时间
parsed_at
2026-10-12 09:31:35
source_bucket
source_bucket
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源对象
source_object
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对象大小
object_size
485417
文件类型
file_type
pdf
姓名
name
叶秀娟
手机号
phone
18770251910
event_name
event_name
ObjectCreated:PutObject
event_time
event_time
2026-10-12T09:31:31.000Z
region
region
cn-hangzhou
etag
etag
073DDE203DDD2B5AEC4A984AEFD4121A
文本长度
text_length
1821
parsed_result
parsed_result
JSON
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"basic_info": {
"name": "叶秀娟",
"gender": null,
"phone": "18770251910",
"email": "18770251910@163.com",
"age": "26",
"birth_date": null,
"location": "深圳市龙岗区",
"work_years": "3.0"
},
"education": [
{
"school": "江西科技师范大学",
"major": "电子信息工程",
"degree": "本科",
"graduation_year": "2023"
}
],
"job_intention": {
"expected_position": "FPGA工程师",
"expected_salary": "13K-16K",
"expected_city": null,
"availability": null
},
"skills": [
"Verilog",
"Quartus",
"Vivado",
"ModelSim",
"数字信号处理(DSP)",
"滤波器设计",
"傅里叶变换(FFT)",
"Python",
"千兆以太网",
"万兆以太网",
"PCIe",
"AD数据采集",
"DDR4缓存设计",
"FPGA驱动程序编写及调试"
],
"work_experience": [
{
"company": "中软国际有限公司",
"position": "FPGA工程师",
"duration": "2023\/08 - 2023\/12",
"description": "1.主导FPGA逻辑架构的设计工作,实现系统的功能定义。2.设计并实现FPGA上的通信接口,如千兆以太网,万兆以太网,PCIe等高速接口。3.设计并实现AD数据采集FPGAPL端的DDR4缓存。"
},
{
"company": "江苏润和软件股份有限公司",
"position": "FPGA工程师",
"duration": "2023\/12 - Present",
"description": "1.负责FPGA驱动程序的编写及调试,确保芯片正常工作。2.基于FPGA实现信号多种型号ADC信号采集以及数字信号处理相关算法(FIR、FFT、STFT、polyphasefir、unwrap、RVS等算法),处理后的数据通过高速接口传出并利用python进行算法验证。3.维护和优化现有FPGA程序,提高系统稳定性和性能。4.协同团队成员完成项目任务,确保项目按时交付。"
}
],
"project_experience": [
{
"name": "基于FPGA的宽带QPSK信号实时解调还原系统",
"role": "FPGA工程师",
"duration": "2026\/04 - 2026\/07",
"description": "项目基于XilinxFPGA平台,采用250MSPS\/12bitADC对115MHz单音与60MHzQPSK混合信号进行正交采样。针对高速采集引入的IQ非正交性问题,设计了自适应延迟补偿与相位校正算法,确保两路信号的正交性。在此基础上,构建了完整的频域处理流水线:通过复数分段FFT与频谱搬移(FFTShift)实现频域匹配滤波,结合重叠保留法(Overlap-Add)与归一化处理,高效完成了时域卷积运算。同时,设计了残余频差纠正与下采样模块,精准补偿收发端频偏。最终,解调数据通过1GUDP以太网实时上传至上位机进行验证。系统有效解决了高速通信中IQ不平衡与频偏干扰问题。"
},
{
"name": "基于FPGA的DAS实时解调系统",
"role": "FPGA工程师",
"duration": "2025\/05 - 2025\/12",
"description": "项目基于XilinxFPGA平台,针对DAS分布式光纤传感中瑞利散射信号微弱、相位易跳变的难题,搭建了基于250MSPS\/4通道ADC的双偏振信号高速采集与实时解调平台。设计了匹配滤波+16\/128阶FIR的分级降噪链路,结合RVS旋转矢量求和算法实现双偏振融合,有效提升弱信号完整性。针对相位不连续问题,配置解缠绕模块修复[-π,π]跳变,还原连续相位曲线。系统通过万兆网\/PCIe上传解调数据至QT上位机实时显示,并支持1G网口远程下发滤波系数等指令,实现闭环参数可控。"
}
],
"certifications": [
"FPGA中级工程师证书",
"大学英语六级"
],
"self_evaluation": "1.熟练掌握Verilog硬件描述语言,能够独立进行FPGA逻辑电路设计编程。2.熟练使用Quartus、Vivado等FPGA开发环境及ModelSim等仿真工具。3.具备数字信号处理(DSP)基础知识,熟悉滤波器、傅里叶变换等概念。4.具备良好的团队合作精神和沟通能力,能够与团队成员共同解决项目中的难题。"
}
output_key
output_key
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状态
status
success
error_message
error_message
无数据
raw_event
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创建时间
created_at
2026-10-12 17:33:05