简历解析
#1204
记录详情
1-6acdd144-15409e-ce5170ce4cd9
success
2026-10-13 14:38:36
ID
id
1204
请求 ID
request_id
1-6acdd144-15409e-ce5170ce4cd9
解析时间
parsed_at
2026-10-13 06:35:52
source_bucket
source_bucket
langbowei-static
源对象
source_object
resumes/1-6acdd144-15409e-ce5170ce4cd9__widget_1704704635359_merged.png
对象大小
object_size
379230
文件类型
file_type
png
姓名
name
姚谦
手机号
phone
无数据
event_name
event_name
ObjectCreated:PutObject
event_time
event_time
2026-10-13T06:35:49.000Z
region
region
cn-hangzhou
etag
etag
EC1524C81997A3AEC5CD59660C552E7D
文本长度
text_length
2028
parsed_result
parsed_result
JSON
{
"basic_info": {
"name": "姚谦",
"gender": "男",
"phone": null,
"email": null,
"age": "27",
"birth_date": null,
"location": "成都",
"work_years": "3.6"
},
"education": [
{
"school": "西南石油大学",
"major": "通信工程",
"degree": "本科",
"graduation_year": "2022"
}
],
"job_intention": {
"expected_position": "FPGA工程师",
"expected_salary": "面议",
"expected_city": null,
"availability": null
},
"skills": [
"图像\/信号处理",
"色彩转换\/缩放\/HDR算法",
"低延迟架构",
"MIPI\/LVDS\/PCIe接口驱动与解包",
"10G\/25G\/HDMI\/DP高速协议",
"DDR3\/4 MIG",
"AXI总线",
"多优先级仲裁设计",
"ILA\/SignalTap调试",
"复杂时序收敛",
"Quartus\/Vivado",
"Arria10\/Agilex7\/Zynq器件",
"Verilog\/VHDL",
"Camera Link\/SDI\/BT1120",
"跨时钟域(CDC)设计",
"万兆以太网"
],
"work_experience": [
{
"company": "成都光稳科技股份有限公司",
"position": "FPGA 工程师",
"duration": "2026\/03 - Present",
"description": "1. 负责 MIPI, LVDS, Camera Link, SDI, BT1120 等异构图像传感器的驱动与协议解包,完成跨时钟域(CDC)对齐与行场同步提炼,保证多路视频无丢帧采集。\n2. 基于 MIG 搭建 DDR3 帧缓冲架构,搭建三帧缓冲机制,以实现对不同帧率图像传感器的适应。\n3. 搭建 PCIe 架构实现 FPGA 与 NPU 的多路传感器图像数据传输,设计 0 帧延迟机制降低数据传输延迟。\n4. 跨平台结构设计,实现不同平台(Xilinx & Anlogic)间的数据传输。"
},
{
"company": "卡莱特云科技股份有限公司",
"position": "FPGA 工程师",
"duration": "2023\/03 - 2026\/03",
"description": "1. 深耕于超高清视频显示与传输领域,主导\/参与过多款高性能发送卡产品的逻辑设计与调测。\n2. 精通 VHDL\/Verilog,具备大型项目代码规范化编写能力,熟悉高速串行接口(SERDES)应用,对万兆以太网、DDR3\/4 多端口存储控制、视频缩放算法有深入理解。\n3. 独立完成从需求分析、方案设计、接口测试、RTL 编码到硬件级调试及性能优化的全流程经验。"
}
],
"project_experience": [
{
"name": "基于 Altera Arria10 平台的双 4K 超高清全彩发送卡开发",
"role": "FPGA工程师",
"duration": "2023\/03 - Present",
"description": "负责 4x10G SFP+ 接口层逻辑设计,采用 Altera Transceiver Native PHY 实现,保证数据在长距离传输下的低误码率。设计基于 DDR3 的多端口缓存管理模块,通过动态分配地址映射策略增加 DDR3 实际利用率,优化读写优先级添加仲裁逻辑提升带宽利用率。处理多个异步时钟域数据交互,利用 FIFO 确保数据完整性,在资源占用率 80% 情况下解决 240MHz 核心频率下的时序违例问题。优化整体结构将输入到输出逻辑延迟控制在 0 帧。优化底图结构、分时复用模块等将 ram 及逻辑资源占用降低 10%,提高 Fmax。成功研发新一代 LED 发送卡,支持双口 4K@60Hz 多图层输入及多路万兆光纤输出和 HDMI 回显输出,解决大分辨率下数据同步与超低延迟传输问题。"
}
],
"certifications": [],
"self_evaluation": ""
}
output_key
output_key
parsed/resumes/1-6acdd144-15409e-ce5170ce4cd9__widget_1704704635359_merged.png.parsed.json
状态
status
success
error_message
error_message
无数据
raw_event
raw_event
JSON
{
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"eventSource": "acs:oss",
"eventTime": "2026-10-13T06:35:49.000Z",
"eventVersion": "1.0",
"oss": {
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"name": "langbowei-static",
"ownerIdentity": "1748673497100614",
"virtualBucket": ""
},
"object": {
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"eTag": "EC1524C81997A3AEC5CD59660C552E7D",
"key": "resumes\/1-6acdd144-15409e-ce5170ce4cd9__widget_1704704635359_merged.png",
"objectMeta": {
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},
"size": 379230
},
"ossSchemaVersion": "1.0",
"ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
},
"region": "cn-hangzhou",
"requestParameters": {
"sourceIPAddress": "172.16.0.122"
},
"responseElements": {
"requestId": "6ACDD145C050393837EF6B88"
},
"userIdentity": {
"principalId": "300034963247836315"
}
}
]
}
创建时间
created_at
2026-10-13 14:38:36