{
    "basic_info": {
        "name": "李佳聪",
        "gender": null,
        "phone": "18142542482",
        "email": "1318093941@qq.com",
        "age": "28",
        "birth_date": null,
        "location": "广东省深圳市",
        "work_years": "6.2"
    },
    "education": [
        {
            "school": "吉林大学",
            "major": "测控技术与仪器",
            "degree": "本科",
            "graduation_year": "2020\/07"
        }
    ],
    "job_intention": {
        "expected_position": "硬件\/逻辑开发",
        "expected_salary": null,
        "expected_city": null,
        "availability": null
    },
    "skills": [
        "Vivado (xilinx IDE)",
        "TD (Anlogic IDE)",
        "Pango (IDE)",
        "Diamond (Lattice IDE)",
        "Quartus (Altera IDE)",
        "modelsim",
        "wireshark",
        "Verilog",
        "VHDL",
        "C语言",
        "shell",
        "python",
        "示波器",
        "逻辑分析仪",
        "万用表",
        "数字电源"
    ],
    "work_experience": [
        {
            "company": "长虹",
            "position": "产品经理",
            "duration": "2020\/07 - 2021\/10",
            "description": "负责机顶盒海外产品线的产品设计与维护工作。负责应标投标，组织软件与硬件完成产品开发，测试，认证，生产等工作。"
        },
        {
            "company": "华为",
            "position": "硬件维护工程师",
            "duration": "2021\/11 - 2023\/06",
            "description": "负责定位骨干路由器的现网问题，主要分析DRMOS等二次电源问题。负责分析现网故障件的硬件问题，定位问题根因50+，给出改进方案并跟踪落地。负责现网补丁包的测试工作。"
        },
        {
            "company": "华为",
            "position": "逻辑工程师",
            "duration": "2023\/07 - 2025\/11",
            "description": "组织进行部门的原理图检视工作，总检视意见400+，个人提出检视意见50+。作为逻辑板主，负责两块单板的逻辑代码开发、验证和版本维护。逻辑代码主要包括单板电源上下电管理及告警模块、复位管理模块、IIC模块（master）、SPI转IIC模块、串口模块、外部PLL配置加载模块、命令控制字模块等等。覆盖3片CPLD与1片FPGA。开发后期兼任硬件板主，负责单板功能与逻辑代码的验证，输出FMEA和FIT测试用例1000+，完成了逻辑功能白盒验证，输出了FMEA、FIT和白盒测试报告，组织完成了测试评审验收工作；定位解决单板硬件问题单100+。主导完成了装备测试，包括装备FT，serdes扫参，温循夹具的导入验证。解决试制、小批量、批量加工时的单板硬件问题，赴客户现场开局，保障了产品开发、测试、生产与开局全流程交付。"
        },
        {
            "company": "卡莱特",
            "position": "FPGA开发工程师",
            "duration": "2025\/11 - 2026\/09",
            "description": "实现视频处理模块代码定制需求，定位历史代码bug。其中通用模块包括SGMII、DDR读写调度模块、高速SerDes、XGMII等。独立完成了无线传输单板的开发调试工作，完成交付。独立完成了高速SerDes PCS层逻辑开发。独立完成了serdes的扫参调参工作。独立完成了单板硬件验证，回板调试等工作。"
        }
    ],
    "project_experience": [],
    "certifications": [],
    "self_evaluation": "我是吉林大学工科专业毕业生，从大学开始学习开发单板硬件与FPGA（大创和毕设），后续工作中也完成了很多硬件\/逻辑开发工作，我个人热爱硬件与逻辑相关工作，因此希望找一份硬件\/逻辑开发工作。我具有6年工作经验，做过产品经理，也做过开发，测试，维护工作，积累了丰富的工作技能，对于产品全流程的生命周期比较了解。本人性格偏外向，情绪稳定，工作态度积极，目前定居广东，个人情况稳定。"
}

{
    "events": [
        {
            "eventName": "ObjectCreated:PutObject",
            "eventSource": "acs:oss",
            "eventTime": "2026-10-14T08:59:45.000Z",
            "eventVersion": "1.0",
            "oss": {
                "bucket": {
                    "arn": "acs:oss:cn-hangzhou:1748673497100614:langbowei-static",
                    "name": "langbowei-static",
                    "ownerIdentity": "1748673497100614",
                    "virtualBucket": ""
                },
                "object": {
                    "deltaSize": 264677,
                    "eTag": "7D5F32A24F1E1C6778987D181DB3E3AF",
                    "key": "resumes\/1-6acf447a-15694b-36c068744215__widget_1704704635359_0.pdf",
                    "objectMeta": {
                        "mimeType": "application\/pdf"
                    },
                    "size": 264677
                },
                "ossSchemaVersion": "1.0",
                "ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
            },
            "region": "cn-hangzhou",
            "requestParameters": {
                "sourceIPAddress": "172.16.0.126"
            },
            "responseElements": {
                "requestId": "6ACF4481A5ABC23735B8683C"
            },
            "userIdentity": {
                "principalId": "300034963247836315"
            }
        }
    ]
}