简历解析
#1296
记录详情
1-6ad7347a-152d7d-89ff4c3ea32c
success
2026-10-20 17:31:17
ID
id
1296
请求 ID
request_id
1-6ad7347a-152d7d-89ff4c3ea32c
解析时间
parsed_at
2026-10-20 09:29:34
source_bucket
source_bucket
langbowei-static
源对象
source_object
resumes/1-6ad7347a-152d7d-89ff4c3ea32c__widget_1704704635359_0.pdf
对象大小
object_size
275136
文件类型
file_type
pdf
姓名
name
李源清
手机号
phone
13479976566
event_name
event_name
ObjectCreated:PutObject
event_time
event_time
2026-10-20T09:29:31.000Z
region
region
cn-hangzhou
etag
etag
CEF945A11C511F2C4C57799CA69E0210
文本长度
text_length
1331
parsed_result
parsed_result
JSON
{
"basic_info": {
"name": "李源清",
"gender": "",
"phone": "13479976566",
"email": "lee20230701@163.com",
"age": "",
"birth_date": "1998\/09",
"location": "",
"work_years": "3.0"
},
"education": [
{
"school": "江西水利电力大学",
"major": "电子信息",
"degree": "硕士",
"graduation_year": "2023"
},
{
"school": "萍乡学院",
"major": "电子信息工程",
"degree": "本科",
"graduation_year": "2020"
}
],
"job_intention": {
"expected_position": "FPGA开发工程师",
"expected_salary": "",
"expected_city": "",
"availability": ""
},
"skills": [
"VerilogHDL",
"时钟复位架构设计",
"跨时钟域CDC处理",
"异步FIFO",
"握手机制",
"图像采集",
"缓存控制",
"接口逻辑设计",
"Vivado",
"Efinity",
"时序约束",
"时序分析与收敛调试",
"AXI4总线协议",
"DDR",
"HyperRAM",
"存储控制器开发",
"读写仲裁优化",
"ModelSim",
"Testbench",
"MATLAB",
"CMOS",
"红外传感器",
"DR平板探测器",
"采集芯片配置",
"板级问题定位",
"量产故障排查"
],
"work_experience": [
{
"company": "安健科技(广东)有限公司",
"position": "FPGA工程师",
"duration": "2026\/05 - Present",
"description": "参与DR平板探测器产品预研,负责采集、缓存及以太网传输相关FPGA逻辑开发与系统联调。适配模拟前端ADC采样时序,完成图像数据位宽对齐、帧同步处理与校验;优化DDR多主端口读写仲裁机制,解决突发访问冲突,提升链路稳定性。"
},
{
"company": "浙江大立科技股份有限公司",
"position": "FPGA工程师",
"duration": "2023\/06 - 2026\/04",
"description": "1. 车载红外热像仪组件及小型化测温模组开发:独立负责红外图像采集与处理框架开发,完成LVDS图像接收链路逻辑设计与时序约束分析,实现640×512@30fps图像采集与模拟视频输出;协同ARM端开展MIPICSI-2接口联调;完成Ti60FPGA平台选型及AXI总线访问逻辑优化,存储带宽利用率提升率达10%;基于HyperRAM完成测温数据连续存储;设计基于Flash快速读取的启动加速方案,将上电至图像显示时间由5s缩短至2.5s。\n2. CameraLink图像采集设备开发与交付:独立负责从需求调研、方案设计、RTL开发到整机交付的全流程工作;协调硬件、软件、结构团队完成接口联调与系统集成,支撑产品试产与量产,负责量产阶段的FPGA逻辑问题定位与优化。"
}
],
"project_experience": [
{
"name": "单网口DR长板探测器预研",
"role": "FPGA工程师",
"duration": "2026\/05 - Present",
"description": "参与DR平板探测器产品预研,负责采集、缓存及以太网传输相关FPGA逻辑开发与系统联调。适配模拟前端ADC采样时序,完成图像数据位宽对齐、帧同步处理与校验;优化DDR多主端口读写仲裁机制,解决突发访问冲突,提升链路稳定性。"
},
{
"name": "车载红外热像仪组件及小型化测温模组开发",
"role": "FPGA工程师",
"duration": "2023\/06 - 2026\/04",
"description": "独立负责红外图像采集与处理框架开发,完成LVDS图像接收链路逻辑设计与时序约束分析,实现640×512@30fps图像采集与模拟视频输出。完成LVDS图像接收链路联调及相关时序约束与分析;协同ARM端开展MIPICSI-2接口联调。完成Ti60FPGA平台选型,完成AXI总线访问逻辑优化,存储带宽利用率提升率达10%;基于HyperRAM完成测温数据连续存储;对接ARM完成MIPICSI-2接口联调。设计基于Flash快速读取的启动加速方案,将上电至图像显示时间由5s缩短至2.5s。"
},
{
"name": "CameraLink图像采集设备开发与交付",
"role": "FPGA工程师",
"duration": "2023\/06 - 2026\/04",
"description": "独立负责CameraLink图像采集设备从需求调研、方案设计、RTL开发到整机交付的全流程工作。协调硬件、软件、结构团队完成接口联调与系统集成,支撑产品试产与量产,负责量产阶段的FPGA逻辑问题定位与优化。"
}
],
"certifications": [],
"self_evaluation": "3年+FPGA开发经验,深耕红外热成像、医疗DR平板探测器两大垂直赛道,具备从需求拆解、RTL逻辑设计、CDC与时序收敛、仿真验证到板级联调、产品量产交付的全流程能力。先后主导\/参与多款红外成像设备落地,擅长高速图像数据通路设计、存储访问仲裁优化与高速接口联调,具备跨团队协同推进项目的能力。"
}
output_key
output_key
parsed/resumes/1-6ad7347a-152d7d-89ff4c3ea32c__widget_1704704635359_0.pdf.parsed.json
状态
status
success
error_message
error_message
无数据
raw_event
raw_event
JSON
{
"events": [
{
"eventName": "ObjectCreated:PutObject",
"eventSource": "acs:oss",
"eventTime": "2026-10-20T09:29:31.000Z",
"eventVersion": "1.0",
"oss": {
"bucket": {
"arn": "acs:oss:cn-hangzhou:1748673497100614:langbowei-static",
"name": "langbowei-static",
"ownerIdentity": "1748673497100614",
"virtualBucket": ""
},
"object": {
"deltaSize": 275136,
"eTag": "CEF945A11C511F2C4C57799CA69E0210",
"key": "resumes\/1-6ad7347a-152d7d-89ff4c3ea32c__widget_1704704635359_0.pdf",
"objectMeta": {
"mimeType": "application\/pdf"
},
"size": 275136
},
"ossSchemaVersion": "1.0",
"ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
},
"region": "cn-hangzhou",
"requestParameters": {
"sourceIPAddress": "172.16.0.132"
},
"responseElements": {
"requestId": "6AD7347A13FBF93739809185"
},
"userIdentity": {
"principalId": "300034963247836315"
}
}
]
}
创建时间
created_at
2026-10-20 17:31:17