简历解析
#1318
记录详情
1-6ad9806f-1514eb-5d858f8c7df7
success
2026-10-22 11:19:54
ID
id
1318
请求 ID
request_id
1-6ad9806f-1514eb-5d858f8c7df7
解析时间
parsed_at
2026-10-22 03:18:17
source_bucket
source_bucket
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源对象
source_object
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对象大小
object_size
185210
文件类型
file_type
pdf
姓名
name
王子义
手机号
phone
无数据
event_name
event_name
ObjectCreated:PutObject
event_time
event_time
2026-10-22T03:18:14.000Z
region
region
cn-hangzhou
etag
etag
A2D660D06AF821F402B5A405AF3E0421
文本长度
text_length
3532
parsed_result
parsed_result
JSON
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"basic_info": {
"name": "王子义",
"gender": "男",
"phone": null,
"email": null,
"age": "27",
"birth_date": null,
"location": "武汉",
"work_years": "3.3"
},
"education": [
{
"school": "长江大学",
"major": "无线电物理",
"degree": "硕士",
"graduation_year": "2023"
},
{
"school": "湖北第二师范学院",
"major": "电子信息科学与技术",
"degree": "本科",
"graduation_year": "2020"
}
],
"job_intention": {
"expected_position": "FPGA工程师",
"expected_salary": "面议",
"expected_city": "武汉",
"availability": null
},
"skills": [
"Verilog",
"ISP算法硬件化",
"软核C驱动开发",
"MIPI\/LVDS\/USB\/GVSP调试",
"DDR3控制器设计",
"AXI\/APB\/Avalon总线设计",
"RISC-V软核开发",
"国产化FPGA平台适配",
"Modelsim仿真",
"Vivado\/Procise",
"Java算法仿真"
],
"work_experience": [
{
"company": "xxx科技公司",
"position": "FPGA高级工程师",
"duration": "2026\/03-Present",
"description": "负责工业相机开发过程中DDR3模块的相关功能实现,搭建DDR3实时数据交互的基础运行环境;完成DDR3与图像采集、处理模块之间的实时数据交互逻辑调试;针对丢数、传输卡顿问题进行优化,提升数据交互稳定性与可靠性。"
},
{
"company": "博宇光电",
"position": "FPGA算法工程师",
"duration": "2024\/04-2026\/03",
"description": "跨平台系统架构设计与国产化适配,在复旦微、易灵思、智多晶等平台从零搭建SoC系统;研发红外核心算法及图像增强处理算法;自研低功耗DDR3控制器及视频接口IP;进行软核软件开发及外设芯片驱动调试;整合多元化视频输出方案并进行系统级联调。"
},
{
"company": "武汉酷锘",
"position": "FPGA算法工程师",
"duration": "2023\/06-2024\/03",
"description": "负责智能硬件\/消费电子方向的FPGA算法相关研发工作,高效落地并完成公司分配的各项研发任务,配合团队完成相关研发环节的落地验证工作。"
}
],
"project_experience": [
{
"name": "工业相机图像成像系统",
"role": "技术负责人",
"duration": "2026\/03-Present",
"description": "从零搭建基于易灵思平台的图像成像系统,设计AMBA总线架构,集成RISC-V、ISP及外设IP;自研AXI互联、APB转Avalon_mm、DMA等关键IP;实现完整的ISP图像处理系统及软核部分设计;进行去平台化IP设计及算法设计;主导硬件选型及团队建设。"
}
],
"certifications": [],
"self_evaluation": "统招本硕,4年FPGA开发经验,深耕红外机芯及工业相机开发。核心ISP算法硬件化能力强,精通Verilog,独立实现NUC、滤波、AGC等ISP全流程。具备软核C驱动编写及上下位机联调经验,有带团队攻坚经验,能适应研发双关期压力。具备MIPI、LVDS、USB及GVSP网口等调试经验,自研DDR3控制器及AXI总线等IP,能跨平台从零搭建系统。"
}
output_key
output_key
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状态
status
success
error_message
error_message
无数据
raw_event
raw_event
JSON
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创建时间
created_at
2026-10-22 11:19:54