简历解析详情

简历解析 #1419

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请求 ID
1-6ae2ec2f-154172-b6e60d374d01
状态
success
创建时间
2026-10-29 14:51:49
ID id
1419
请求 ID request_id
1-6ae2ec2f-154172-b6e60d374d01
解析时间 parsed_at
2026-10-29 06:48:19
source_bucket source_bucket
langbowei-static
源对象 source_object
resumes/1-6ae2ec2f-154172-b6e60d374d01__widget_1704704635359_merged.png
对象大小 object_size
851943
文件类型 file_type
png
姓名 name
张润民
手机号 phone
18650656723
event_name event_name
ObjectCreated:PutObject
event_time event_time
2026-10-29T06:48:16.000Z
region region
cn-hangzhou
etag etag
F9EB39FE225D8F571EADA49C9798D3A8
文本长度 text_length
4528
parsed_result parsed_result
JSON
{
    "basic_info": {
        "name": "张润民",
        "gender": "男",
        "phone": "18650656723",
        "email": "632526942@qq.com",
        "age": null,
        "birth_date": "1995",
        "location": "上海",
        "work_years": 6.2
    },
    "education": [
        {
            "school": "沈阳理工大学",
            "major": "电子科学与技术(集成电路设计)",
            "degree": "本科",
            "graduation_year": "2018\/06"
        }
    ],
    "job_intention": {
        "expected_position": "FPGA工程师",
        "expected_salary": "面议",
        "expected_city": "广东省-深圳",
        "availability": null
    },
    "skills": [
        "FPGA开发",
        "信号\/图像处理",
        "LVDS高速接口调试",
        "MIPI CSI",
        "PCIe",
        "高速SerDes链路",
        "时序收敛",
        "Verilog",
        "Vivado",
        "时序约束与时序优化",
        "Xilinx底层原语",
        "DDR",
        "AXI总线",
        "ARM\/MicroBlaze软硬件协同开发",
        "脚本自动化验证",
        "算法建模"
    ],
    "work_experience": [
        {
            "company": "京微齐力科技有限公司",
            "position": "FPGA工程师",
            "duration": "2024\/05 - Present",
            "description": "主要负责IP核架构设计与RTL实现、底层原语设计实现及兼容设计、验证环境搭建与测试用例开发、接口协议定义等。完成Multiplier、DMA、AXI4-Interconnect等多个IP核设计;完成基于京微齐力器件底层资源的原语设计;完成工业相机处理系统、MIPI DSI\/LVDS双接口点屏工程等。"
        },
        {
            "company": "北京赛博兴安科技有限公司",
            "position": "FPGA工程师",
            "duration": "2020\/11 - 2024\/05",
            "description": "主要负责FPGA项目设计,参与方案评审与芯片选型,完成硬件架构设计、RTL实现及约束验证,负责系统级调试与大型联试。完成HK、DZ、K三个研究所重点项目FPGA产品研发,覆盖硬件架构设计、RTL实现、约束验证到系统级调试全流程。"
        },
        {
            "company": "北京六合联创科技有限公司",
            "position": "FPGA工程师",
            "duration": "2018\/08 - 2020\/10",
            "description": "负责FPGA设计、开发、调试,配合硬件\/软件工程师联合开发,完成技术储备型课题任务。完成直线超导加速器系统的FPGA设计研发及常带测向预处理系统的FPGA设计研发。"
        }
    ],
    "project_experience": [
        {
            "name": "工业相机处理系统",
            "role": "FPGA工程师",
            "duration": null,
            "description": "基于京微齐力HME-PV65平台适配索尼IMX568全局快门传感器,经MIPI CSI-2四通道接口接收图像数据,自研CSI-2接收协议层写入DDR4三帧轮转缓存;水平双分区ISP流水线实时处理像素流,输出经PCIe Gen3 ×4硬核C2H DMA流式直发主机;板载Cortex-M3完成传感器配置与多时钟域设计。"
        },
        {
            "name": "MIPI DSI\/LVDS 双接口点屏工程",
            "role": "FPGA工程师",
            "duration": null,
            "description": "基于HME-H7平台实现MIPI DSI与LVDS双接口点屏:自研DSI Host TX与D-PHY TX,完成Video Mode视频流打包、CRC\/ECC校验及状态切换;LVDS输出经OSERDES串并转换,兼容VESA\/JEIDA两种位映射标准,可直驱主流工业面板。"
        },
        {
            "name": "MIPI D-PHY\/CSI-2 自研工程",
            "role": "FPGA工程师",
            "duration": null,
            "description": "基于HME-H7平台自研MIPI D-PHY与CSI-2完整接收链路,D-PHY RX划分为LP\/HS检测、链路时钟DDR解串、SoT字节对齐三层;CSI-2协议层实现包头解析、ECC\/CRC校验等,输出PP1 8-bit像素流,已完成TX\/RX loopback仿真验证。"
        },
        {
            "name": "视频采集系统",
            "role": "FPGA工程师",
            "duration": null,
            "description": "HDMI信号解码后进入FPGA帧缓冲模块写入DDR3;读侧经缩放器实时抽取数据,PCIe与光纤两路读出通过AXI互联仲裁共享DDR带宽。FDMA控制器将视频流高效写入DDR3物理层;XDMA IP通过C2H DMA通道将视频帧直传主机内存,形成完整闭环。"
        },
        {
            "name": "3D ZS 设备",
            "role": "FPGA工程师",
            "duration": null,
            "description": "系统采用双通路架构:业务数据通路通过4路SGMII接收终端数据,经DDR缓存、协议解析、算法运算后转发;管理命令通路接收管理命令并下发参数。完成项目研发,通过初样\/正样实验及大型联试。"
        },
        {
            "name": "6U 适配项目",
            "role": "FPGA工程师",
            "duration": null,
            "description": "业务通路承载RapidIO与算法卡间的高速数据交换,解决跨接口带宽匹配与流控衔接;管理通路经SGMII接入、RGMII上联CPU完成命令交互与状态上报。完成初样\/正样实验及大型联试。"
        },
        {
            "name": "CJY 数据接收设备",
            "role": "FPGA工程师",
            "duration": null,
            "description": "FPGA数据采集系统,透明接入多种数据链路并实时采集提取数据。实现RGMII接口、协议解析、分段处理、接口适配与基于优先级的调度,支持双向命令交互。系统已通过验收并完成十余种协议格式的程序开发与现场调试。"
        }
    ],
    "certifications": [],
    "self_evaluation": ""
}
output_key output_key
parsed/resumes/1-6ae2ec2f-154172-b6e60d374d01__widget_1704704635359_merged.png.parsed.json
状态 status
success
error_message error_message
无数据
raw_event raw_event
JSON
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创建时间 created_at
2026-10-29 14:51:49