简历解析
#384
记录详情
1-6a6884f3-15c718-b651364ceb04
success
2026-07-28 18:33:08
ID
id
384
请求 ID
request_id
1-6a6884f3-15c718-b651364ceb04
解析时间
parsed_at
2026-07-28 10:31:17
source_bucket
source_bucket
langbowei-static
源对象
source_object
resumes/1-6a6884f3-15c718-b651364ceb04__widget_1704704635359_0.pdf
对象大小
object_size
327519
文件类型
file_type
pdf
姓名
name
孙玉昆
手机号
phone
15039689573
event_name
event_name
ObjectCreated:PutObject
event_time
event_time
2026-07-28T10:31:15.000Z
region
region
cn-hangzhou
etag
etag
A5722F145564FBE8606BC10D38101B79
文本长度
text_length
3741
parsed_result
parsed_result
JSON
{
"basic_info": {
"name": "孙玉昆",
"gender": "男",
"phone": "15039689573",
"email": "syker@foxmail.com",
"age": "26",
"birth_date": "",
"location": "河南省驻马店市",
"work_years": "1.2"
},
"education": [
{
"school": "北京信息科技大学",
"major": "仪器科学与技术",
"degree": "硕士",
"graduation_year": "2026"
},
{
"school": "景德镇陶瓷大学",
"major": "自动化",
"degree": "本科",
"graduation_year": "2022"
}
],
"job_intention": {
"expected_position": "FAE",
"expected_salary": "",
"expected_city": "",
"availability": ""
},
"skills": [
"AD",
"嘉立创EDA",
"Vivado",
"Quartus II",
"Keil",
"FPGA",
"ARM",
"LDO",
"DCDC",
"Verilog",
"SystemVerilog",
"STA",
"C",
"C#",
"千兆以太网 UDP",
"AXI4",
"SPI",
"I²C",
"UART",
"SDRAM\/DDR3",
"LVDS",
"CMOS",
"DAC",
"ILA",
"VIO"
],
"work_experience": [
{
"company": "北京超维景生物科技有限公司",
"position": "硬件组实习生",
"duration": "2024\/08 - 2025\/02",
"description": "参与基于ZYNQ平台实现光信号采集、图像处理与千兆以太网传输全链路开发;参与SN600高端医疗成像系统核心数据采集与传输链路开发,关键性能指标达到预期并实现量产。"
},
{
"company": "梅卡曼德机器人科技股份有限公司",
"position": "相机组FPGA实习生",
"duration": "2025\/08 - 2025\/10",
"description": "参与系统电源模块方案讨论与关键器件选型,协助制作与维护BOM清单;使用AD完成FPGA外围基础电路设计;参与FPGA逻辑开发,开发四通道120MSPS ADC数据采集、DAC驱动控制及千兆以太网UDP协议栈;参与Mech-Eyes LSR-L系列产品sensor的FPGA侧数据采集与验证,包括图像数据采集、LVDS数据眼图训练及数据多通道对齐。"
}
],
"project_experience": [
{
"name": "四路高速ADC采集处理与千兆以太网实时传输系统",
"role": "核心开发",
"duration": "2024\/08 - 2025\/02",
"description": "基于ZYNQ平台实现光信号采集→图像处理→千兆以太网传输全链路开发。实现高速AD采样(基于8组LVDS差分对的源同步传输架构,实现四通道120MSPS\/16bit ADC数据的精确同步捕获);实现RGMII接口UDP千兆以太网协议栈,划分四级优先级通道缓冲区,通过优先级加权动态轮询仲裁实现成像数据实时传输。参与开发的SN600高端医疗成像系统已成功通过验证并实现量产。"
},
{
"name": "基于FPGA的FSK信号调制解调系统开发",
"role": "主要负责人",
"duration": "2024\/02 - 2024\/05",
"description": "负责开发基于FPGA的高速通信模块,实现上位机与勘探设备间高可靠性数据通信。完成原有设备PCB原理图提取与功能模块分析;基于Verilog HDL独立完成2FSK调制解调核心代码编写,利用ModelSim进行功能仿真和时序分析;联合上位机开展系统联调,解决时钟抖动和噪声干扰问题。成功实现FSK调制解调功能,误码率低于0.01%,项目一次性验收通过。"
},
{
"name": "基于FPGA的超快采集与控制系统",
"role": "主要负责人",
"duration": "2024\/12 - 2025\/06",
"description": "科技部科技创新2030-重大项目。主导基于Xilinx KU系列FPGA构建“解耦-重构-交互-传输”四位一体的图像处理链路开发。实现5Gsps高速信号解耦与处理,9路子通道3.2ns门控解复用;采用并行计算架构进行图像重构与传输优化,通过AXI4协议实现图像数据高效突发写入DDR缓存;分析STA时序报告,在312.5MHz高主频下完成时序收敛。独立完成超快成像系统研发,实现千赫兹级别稳定成像。"
}
],
"certifications": [
"CET-6"
],
"self_evaluation": "积极乐观,乐于沟通,有耐心,有毅力。闲暇时喜欢慢跑(5KM+),骑行(累计1000KM+)。"
}
output_key
output_key
parsed/resumes/1-6a6884f3-15c718-b651364ceb04__widget_1704704635359_0.pdf.parsed.json
状态
status
success
error_message
error_message
无数据
raw_event
raw_event
JSON
{
"events": [
{
"eventName": "ObjectCreated:PutObject",
"eventSource": "acs:oss",
"eventTime": "2026-07-28T10:31:15.000Z",
"eventVersion": "1.0",
"oss": {
"bucket": {
"arn": "acs:oss:cn-hangzhou:1748673497100614:langbowei-static",
"name": "langbowei-static",
"ownerIdentity": "1748673497100614",
"virtualBucket": ""
},
"object": {
"deltaSize": 327519,
"eTag": "A5722F145564FBE8606BC10D38101B79",
"key": "resumes\/1-6a6884f3-15c718-b651364ceb04__widget_1704704635359_0.pdf",
"objectMeta": {
"mimeType": "application\/pdf"
},
"size": 327519
},
"ossSchemaVersion": "1.0",
"ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
},
"region": "cn-hangzhou",
"requestParameters": {
"sourceIPAddress": "172.16.0.154"
},
"responseElements": {
"requestId": "6A6884F324F1BD36304CA278"
},
"userIdentity": {
"principalId": "300034963247836315"
}
}
]
}
创建时间
created_at
2026-07-28 18:33:08