{
    "basic_info": {
        "name": "陈泓宇",
        "gender": null,
        "phone": "190-0643-6315",
        "email": "1305558326@qq.com",
        "age": "26",
        "birth_date": null,
        "location": "深圳",
        "work_years": "3.0"
    },
    "education": [
        {
            "school": "河南科技大学",
            "major": "测控技术与仪器",
            "degree": "工学学士",
            "graduation_year": "2023\/06"
        }
    ],
    "job_intention": {
        "expected_position": "FPGA开发工程师",
        "expected_salary": null,
        "expected_city": "深圳",
        "availability": null
    },
    "skills": [
        "Verilog",
        "SystemVerilog",
        "SystemVerilog Testbench",
        "UVM",
        "Intel Altera Cyclone V",
        "安路 Anlogic",
        "易灵思 Efinity",
        "紫光同创",
        "GLINK",
        "EtherCAT",
        "CAN",
        "PCIe (DMA)",
        "高速ADC\/编码器采样",
        "高精度PWM",
        "网络同步电流环",
        "跨时钟域 (CDC)",
        "芯片级验证",
        "ARM-FPGA协同",
        "FSBL\/bootloader工程生成 (Vitis\/SDK)",
        "Vivado",
        "Quartus Prime",
        "Efinity",
        "VCS",
        "Verdi",
        "C\/C++",
        "英语 (CET-4)"
    ],
    "work_experience": [
        {
            "company": "固高科技（GoogolTech）",
            "position": "FPGA工程师",
            "duration": "2023\/07 - Present",
            "description": "负责工业网络芯片通信子系统GLINK的RTL设计与SystemVerilog验证，参与需求分析与系统架构定制，支撑伺服控制场景下的GLINK\/EtherCAT\/CAN多总线通信。\n新增同步控制模块，实现外设模块与网络的高精度同步；承接原有FPGA代码完成芯片级验证与代码检查并补充外设模块，该项目已成功流片（Tape-out）。\n跨多产品线交付FPGA方案：伺服驱动器（网络同步电流环、高精度PWM与编码器采样）、PCIe高速数据采集（Zynq+DMA）、印刷套色（安路FPGA+高速ADC\/编码器）、温度采集SOC（安路FPGA+内嵌ARM）等。\n覆盖Altera Cyclone V、紫光等同平台联调与工程移植，包含FSBL\/bootloader生成与ARM-FPGA协同。"
        }
    ],
    "project_experience": [
        {
            "name": "工业网络芯片（GLINK）合作开发",
            "role": "通信子系统FPGA\/验证",
            "duration": "2023\/07 - 2024\/12",
            "description": "与芯片公司合作，面向伺服电机控制完成需求分析与整体系统架构定制；通信侧支持GLINK、EtherCAT、CAN等工业总线。负责GLINK规格整理、RTL编写、SystemVerilog验证与代码调试优化，并新增同步控制模块，实现外设模块与网络的高精度同步。承接原有FPGA代码完成芯片级验证与代码检查、补充外设模块；项目已成功流片。"
        },
        {
            "name": "伺服驱动器FPGA开发",
            "role": "FPGA开发",
            "duration": "2024\/04 - 2024\/05",
            "description": "结合新硬件编写并移植FPGA代码，实现网络同步电流环、高精度PWM输出与高精度编码器采样，协同ARM完成伺服电机闭环控制。"
        },
        {
            "name": "PCIe高速数据采集卡",
            "role": "FPGA开发",
            "duration": "2024\/05 - 2024\/11",
            "description": "基于Xilinx Zynq平台实现100K速率高速数据采集，并通过PCIe DMA传输至上位机进行处理。基于Intel Altera Cyclone V平台修改并移植bootloader工程，完成平台适配。"
        },
        {
            "name": "印刷套色系统",
            "role": "FPGA开发",
            "duration": "2025\/04 - 2026\/06",
            "description": "基于安路（Efinity）FPGA高速采样ADC与编码器数据，实现等距数据采样与套色误差计算。通过网络传输完成光电眼误差计算与印刷套色控制。"
        },
        {
            "name": "温度采集子板SOC开发",
            "role": "FPGA+内嵌ARM开发",
            "duration": "2026\/06 - Present",
            "description": "基于安路FPGA与内嵌ARM开发温度采集模块：FPGA负责与ADC及主板通信，ARM完成温度换算。调试中定位并解决硬件漏电问题，模块支持KTY84、PT100与热电偶多种传感器。"
        },
        {
            "name": "其他项目概要",
            "role": "FPGA开发",
            "duration": "2025\/07 - 2026\/09",
            "description": "瑶光项目（2026\/01-2026\/03）：基于Zynq的空中上网项目，负责FPGA开发并协助客户生成FSBL工程。\nVersal\/UltraScale+控制卡FPGA与ARM联调（2025\/07-2025\/12）。\n软运控PCIe联调（2026\/03-2026\/05）、BITMOVE模块编写调试（2026\/04-2026\/05）。\nGLINK网络芯片项目（2026\/03-2026\/09）、基于紫光FPGA的轴模块项目（2026\/05）、GLINK网络同步测试（2026\/03）。"
        }
    ],
    "certifications": [
        "CET-4（451分）",
        "全国计算机等级考试（NCRE）二级C语言程序设计（良好）"
    ],
    "self_evaluation": "拥有3年FPGA开发经验，现就职于固高科技，深耕工业运动控制与工业网络芯片领域。熟练运用Xilinx（Zynq\/Versal\/UltraScale+）、Intel Altera（Cyclone V）、安路（Anlogic，Efinity）与紫光同创等多厂商FPGA平台，掌握Verilog\/SystemVerilog RTL设计与SystemVerilog验证流程。主导工业网络芯片GLINK从架构定义到成功流片，并具备伺服驱动器、PCIe高速采集、印刷套色、温度采集SOC等端到端交付经验。"
}

{
    "events": [
        {
            "eventName": "ObjectCreated:PutObject",
            "eventSource": "acs:oss",
            "eventTime": "2026-07-28T11:05:39.000Z",
            "eventVersion": "1.0",
            "oss": {
                "bucket": {
                    "arn": "acs:oss:cn-hangzhou:1748673497100614:langbowei-static",
                    "name": "langbowei-static",
                    "ownerIdentity": "1748673497100614",
                    "virtualBucket": ""
                },
                "object": {
                    "deltaSize": 97156,
                    "eTag": "B73F5F1C4E0329A46C80DFA47C5A5C2F",
                    "key": "resumes\/1-6a688d03-15a2cc-810c5c4e15f4__widget_1704704635359_0.pdf",
                    "objectMeta": {
                        "mimeType": "application\/pdf"
                    },
                    "size": 97156
                },
                "ossSchemaVersion": "1.0",
                "ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
            },
            "region": "cn-hangzhou",
            "requestParameters": {
                "sourceIPAddress": "172.16.0.154"
            },
            "responseElements": {
                "requestId": "6A688D032EC305383048A2C2"
            },
            "userIdentity": {
                "principalId": "300034963247836315"
            }
        }
    ]
}