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        "gender": "男",
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        "birth_date": "",
        "location": "深圳",
        "work_years": "0.2"
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        {
            "school": "厦门大学",
            "major": "电子信息",
            "degree": "硕士",
            "graduation_year": "2024\/06"
        },
        {
            "school": "燕山大学",
            "major": "电子科学与技术",
            "degree": "本科",
            "graduation_year": "2020\/06"
        }
    ],
    "job_intention": {
        "expected_position": "",
        "expected_salary": "",
        "expected_city": "",
        "availability": ""
    },
    "skills": [
        "FPGA编程",
        "quartus",
        "modelsim",
        "vitis",
        "vivado",
        "时序分析及约束",
        "数字信号运算处理",
        "IP使用",
        "VBO",
        "DDR",
        "千万兆网",
        "PCIE",
        "AXI总线",
        "JESD204b",
        "GT IP",
        "3D LUT",
        "HDMI",
        "Bayer图像处理",
        "色域校准",
        "Verilog",
        "VHDL",
        "SystemVerilog",
        "python",
        "高速通信接口实现"
    ],
    "work_experience": [
        {
            "company": "深圳康冠科技公司",
            "position": "fpga开发工程师",
            "duration": "2024\/08 - Present",
            "description": "主要负责VBO显示项目当中的接口实现及后续的图像处理。"
        }
    ],
    "project_experience": [
        {
            "name": "基于Verilog的V-by-One协议实现及4K60Hz视频传输显示",
            "role": "FPGA开发工程师",
            "duration": "2024\/08 - Present",
            "description": "1）V-by-One协议Verilog开发与优化，实现4K60Hz视频数据稳定传输显示；\n2）使用8通道4byte模式进行控制数据及像素数据打包传输，可满足10位色深RGB像素数据传输需求；\n3）使用16位的环形移位寄存器进行数据加扰解扰，通过GT IP实现serdes数据的收发。"
        },
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            "duration": "2024\/08 - Present",
            "description": "1）通过四面体插值实现33x33x33 3D LUT算法verilog开发，可实现色彩校正误差控制在0.5以内，满足高端色彩标准；\n2）通过3x3矩阵变换，成功实现源色域到目标色域sRGB、Adobe RGB、DCI-P3、Rec709四种主流色域的精准转换；\n3）整合白平衡调节、Gamma LUT校正及3x3色域矩阵变换，成功实现在不同色域，不同白平衡与Gamma值组合场景的显示模式下平均色差ΔE稳定控制在1.0以内。"
        },
        {
            "name": "基于Verilog的饱和度色域压缩算法开发",
            "role": "FPGA开发工程师",
            "duration": "2024\/08 - Present",
            "description": "1）按照RGB→XYZ→LAB→LCH(饱和度压缩)→LAB→XYZ→RGB数据处理顺序完成色域压缩；\n2）在LCH格式中采用双线性插值获取该色相角H及L亮度下的最大饱和度后进行压缩，完成了对bram资源优化；\n3）可将超出目标色域的高饱和颜色，在保持色相和亮度基本不变的前提下，映射到目标色域内，避免溢色。"
        },
        {
            "name": "PCIE实现1080P视频数据接收及Hdmi显示",
            "role": "FPGA开发工程师",
            "duration": "2024\/08 - Present",
            "description": "1）采用xdma\/Riffa架构实现PCIE2.0数据信号接收；\n2）像素数据通过axi-full数据写总线存储在DDR完成帧缓存；\n3）将数据信号由axi-full读总线读出并传给HDMI总线完成图像传输显示。"
        },
        {
            "name": "ADC\/DAC数据采集项目：基于JESD204B实现AD9371数据收发",
            "role": "FPGA开发工程师",
            "duration": "2024\/08 - Present",
            "description": "1）使用DDS生成4路共128位数据，采样频率61.44M，带宽2.4576G，同axis总线握手后数据传输给到JESD204b IP；\n2）数据链路建立后JESD204b采用4lane，每帧每lane 2个字节，多帧为32形式发送给PHY物理层完成serdes数据的收发；\n3）PHY收发端同AD9371的4路ADC、DAC相连，ADC同DAC互连实现数据环回，接收端结合axis总线握手时序解析出数据。"
        }
    ],
    "certifications": [
        "英语六级(455分)",
        "2017年河北省电赛四旋翼组三等奖",
        "2018年校电赛二等奖",
        "2018年校电赛三等奖",
        "发明专利：一种基于FPGA的超快激光水下远距离通信与探测方法及系统",
        "中国研究生电子设计竞赛华东赛区二等奖",
        "第一届网络安全会议优秀论文"
    ],
    "self_evaluation": "个人能很好地处理自身的负面情绪，让自己更好的投入到学习和工作当中去。具备良好沟通能力及独立解决问题的能力。具有团队协作精神，具备良好沟通能力及独立解决问题的能力。对探索新事物具有深厚的兴趣，能持久保持对工作的热情态度。"
}

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