{
    "basic_info": {
        "name": "刘瑞",
        "gender": "男",
        "phone": "***",
        "email": "***",
        "age": "23",
        "birth_date": "2002\/01",
        "location": "上海市",
        "work_years": "2.9"
    },
    "education": [
        {
            "school": "重庆文理学院",
            "major": "微电子科学与工程",
            "degree": "本科",
            "graduation_year": "2023\/06"
        }
    ],
    "job_intention": {
        "expected_position": "中级\/高级FPGA工程师",
        "expected_salary": "面议",
        "expected_city": "深圳\/苏州\/江苏省",
        "availability": "一个月"
    },
    "skills": [
        "FPGA开发",
        "嵌入式硬件开发",
        "Verilog",
        "C语言",
        "PCB设计",
        "Vivado",
        "Quartus II",
        "Modelsim",
        "Pango Design Suite",
        "Keil",
        "Altium Designer",
        "MATLAB",
        "AXI4",
        "SPI",
        "Ethernet",
        "IIC",
        "RS485",
        "RS232",
        "UART",
        "SCCB",
        "DVP",
        "HDMI",
        "MIPI",
        "LVDS",
        "CameraLink"
    ],
    "work_experience": [
        {
            "company": "剑芯光电",
            "position": "FPGA开发工程师",
            "duration": "2025\/11 - Present",
            "description": "做LCoS驱动开发，1024×1024，1920x1080，2048x2048三种分别率"
        },
        {
            "company": "上海嘉沃光电科技有限公司",
            "position": "FPGA开发工程师",
            "duration": "2023\/11 - 2025\/11",
            "description": "1. 短波红外研发 2. 其它sensor研发。精通FPGA开发,嵌入式硬件开发,熟练使用多种开发工具、仿真和debug调试,掌握Verilog语言和C语言,具有良好的编码风格和习惯。在FPGA开发、电路设计、程序开发、PCB设计等方面具有丰富经验,能够独立完成各种复杂的项目开发任务。"
        },
        {
            "company": "未提及",
            "position": "FPGA开发工程师助理（实习）",
            "duration": "2022\/12 - 2023\/06",
            "description": "协助FPGA工程师完成板卡验证及开发，主导基于ESP32、STM32的项目的开发。参与板卡的外部FLASH、EEPROM、HDMI、以太网等模块的验证程序设计及数据交互程序设计，系统调试等。参与嵌入式系统的软件开发，包括底层驱动编写、系统调试以及性能优化等。"
        }
    ],
    "project_experience": [
        {
            "name": "基于 FPGA 的图像处理",
            "role": "FPGA开发工程师",
            "duration": null,
            "description": "使用 Xilinx 的 MPSOC FPGA 实现 OV5640 分别率为 1280*720 图像采集，DDR4 乒乓缓存，图像处理，HDMI 传输。使用算法包括色彩空间转换、滤波、边缘提取、二值化等。"
        },
        {
            "name": "基于 FPGA 的 Sobel 边缘检测",
            "role": "FPGA开发工程师",
            "duration": null,
            "description": "使用紫光同创 FPGA PG2L100H 实现图像采集，图像 RGB 转 YCbCr，Sobel 计算，高斯滤波、二值化处理，最终通过 SIL9134(HDMI 编码芯片)传输到显示屏。"
        },
        {
            "name": "基于 FPGA 的以太网传输",
            "role": "FPGA开发工程师",
            "duration": null,
            "description": "使用 Xilinx 的 MPSOC FPGA 实现 OV5640 图像采集，并通过以太网接口发送给上位机实时显示。"
        },
        {
            "name": "基于 FPGA 的 DDS 信号发生器",
            "role": "FPGA开发工程师",
            "duration": null,
            "description": "使用 Altera 的 Cydone IV E FPGA 和高速 DA 芯片 AD9708 实现 DDS 信号发生器，通过示波器来观察波形。包含波形存储器模块、DA模块、频率控制模块、相位控制模块和波形控制模块。"
        }
    ],
    "certifications": [
        "FPGA 开发工程师",
        "校级综合奖学金一等奖",
        "优秀学生干部",
        "校级单片机设计竞赛一等奖",
        "校级单片机设计竞赛二等奖",
        "TI 杯电子设计大赛重庆三等奖"
    ],
    "self_evaluation": "具有良好团队合作精神和沟通能力，能够与团队成员和跨部门工程师有效地合作，确保项目的顺利进行。积极追踪FPGA开发领域的新技术和新趋势，以保持技术领先，并将新技术应用到项目开发中，提升产品的竞争力。"
}

{
    "events": [
        {
            "eventName": "ObjectCreated:PutObject",
            "eventSource": "acs:oss",
            "eventTime": "2026-08-13T07:29:31.000Z",
            "eventVersion": "1.0",
            "oss": {
                "bucket": {
                    "arn": "acs:oss:cn-hangzhou:1748673497100614:langbowei-static",
                    "name": "langbowei-static",
                    "ownerIdentity": "1748673497100614",
                    "virtualBucket": ""
                },
                "object": {
                    "deltaSize": 671176,
                    "eTag": "703E862D432B54B3CF35650BC49449CD",
                    "key": "resumes\/1-6a7d7259-159ffb-07bde9cccd28__widget_1704704635359_merged.png",
                    "objectMeta": {
                        "mimeType": "image\/png"
                    },
                    "size": 671176
                },
                "ossSchemaVersion": "1.0",
                "ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
            },
            "region": "cn-hangzhou",
            "requestParameters": {
                "sourceIPAddress": "172.16.0.119"
            },
            "responseElements": {
                "requestId": "6A7D725B6612A43239C71EA8"
            },
            "userIdentity": {
                "principalId": "300034963247836315"
            }
        }
    ]
}