简历解析
#850
记录详情
1-6a8eaddc-15902e-cddb07097493
success
2026-08-26 17:14:46
ID
id
850
请求 ID
request_id
1-6a8eaddc-15902e-cddb07097493
解析时间
parsed_at
2026-08-26 09:12:00
source_bucket
source_bucket
langbowei-static
源对象
source_object
resumes/1-6a8eaddc-15902e-cddb07097493__widget_1704704635359_merged.png
对象大小
object_size
664931
文件类型
file_type
png
姓名
name
武祥兵
手机号
phone
13571489270
event_name
event_name
ObjectCreated:PutObject
event_time
event_time
2026-08-26T09:11:58.000Z
region
region
cn-hangzhou
etag
etag
4CB92DF2EE55F7D827E8A716E730C11D
文本长度
text_length
3075
parsed_result
parsed_result
JSON
{
"basic_info": {
"name": "武祥兵",
"gender": "男",
"phone": "13571489270",
"email": "wuxiangbing07@163.com",
"age": null,
"birth_date": "1998",
"location": "陕西省-西安",
"work_years": 3.1
},
"education": [
{
"school": "西安电子科技大学",
"major": "航天工程",
"degree": "硕士",
"graduation_year": "2023\/06"
},
{
"school": "西安建筑科技大学",
"major": "电子信息科学与技术",
"degree": "本科",
"graduation_year": "2020\/07"
}
],
"job_intention": {
"expected_position": "FPGA工程师",
"expected_salary": "面议",
"expected_city": "广东省-深圳",
"availability": null
},
"skills": [
"Verilog",
"数字电路",
"Tcl",
"MATLAB",
"Vivado",
"Xilinx FPGA",
"Quartus",
"Intel FPGA",
"Modelsim",
"紫光 FPGA",
"LVDS",
"BASE-R",
"XSGMII",
"RGMII",
"MIPI",
"SPI",
"IIC",
"GT",
"GTY",
"GTH",
"DDR4",
"时序分析与约束",
"资源评估",
"原理图评审"
],
"work_experience": [
{
"company": "西安诺瓦星云科技股份有限公司",
"position": "FPGA工程师",
"duration": "2023\/07 - Present",
"description": "负责视频与显示控制相关的FPGA开发、协议统一、资源评估、原理图评审及疑难问题排查等工作。主导Unico协议切换、影院项目及物料导入等核心项目,并沉淀标准化文档赋能团队。"
}
],
"project_experience": [
{
"name": "Unico 协议切换",
"role": "核心开发",
"duration": "2023\/09 - 2024\/08",
"description": "负责产品衍生定制产品的功耗与资源评估;统一产品线协议,修改协议并自测,处理代码适配性问题;进行MIPI接口回显调试及RGMII调相;参与资源、功耗评估和原理图评审,进行替代料验证。所负责项目获产品线质量排名第二,独立处理90%转测问题。"
},
{
"name": "影院项目",
"role": "FPGA领域负责人\/核心开发",
"duration": "2024\/09 - Present",
"description": "负责全链路问题处理、工程资源优化和版本管理;负责项目计划拆解、进度把控及风险监控;评估DDR带宽与资源占用,审核原理图;开发1:2 LVDS模块,兼容两种时钟频率输入;基于GTY配合开发1G网口和10G光口产品;通过XDC约束实现影院工程合一,降低30%工程维护成本。解决XSGMII状态机跳转异常及Serdes源不识别等疑难问题。"
},
{
"name": "物料导入",
"role": "主导",
"duration": "2023\/12 - Present",
"description": "主导光模块替代以降低成本;调试7系列GT的TX\/RX眼图参数控制信号,找到最佳参数并输出眼图调试经验手册;眼图程序经高低温测试无误码,导入产品无闪屏及客诉问题。"
}
],
"certifications": [
"中级FPGA工程师评级"
],
"self_evaluation": "具备3年视频显示行业FPGA岗位经验,熟悉FPGA全套开发流程,能够快速进行代码分析与开发。具备较强的工程攻坚与问题闭环能力,善于从底层原理和正向代码分析定位疑难问题,并沉淀为标准化文档赋能团队。工作期间获得公司中级FPGA工程师评级,通过《北极星》公司级别培训,并获得客户感谢信。"
}
output_key
output_key
parsed/resumes/1-6a8eaddc-15902e-cddb07097493__widget_1704704635359_merged.png.parsed.json
状态
status
success
error_message
error_message
无数据
raw_event
raw_event
JSON
{
"events": [
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"eventName": "ObjectCreated:PutObject",
"eventSource": "acs:oss",
"eventTime": "2026-08-26T09:11:58.000Z",
"eventVersion": "1.0",
"oss": {
"bucket": {
"arn": "acs:oss:cn-hangzhou:1748673497100614:langbowei-static",
"name": "langbowei-static",
"ownerIdentity": "1748673497100614",
"virtualBucket": ""
},
"object": {
"deltaSize": 664931,
"eTag": "4CB92DF2EE55F7D827E8A716E730C11D",
"key": "resumes\/1-6a8eaddc-15902e-cddb07097493__widget_1704704635359_merged.png",
"objectMeta": {
"mimeType": "image\/png"
},
"size": 664931
},
"ossSchemaVersion": "1.0",
"ruleId": "6ace21aabfd5f4f41034504922b3ff7128aa76bb"
},
"region": "cn-hangzhou",
"requestParameters": {
"sourceIPAddress": "172.16.0.129"
},
"responseElements": {
"requestId": "6A8EADDE1652423231EF90C9"
},
"userIdentity": {
"principalId": "300034963247836315"
}
}
]
}
创建时间
created_at
2026-08-26 17:14:46