简历解析
#967
记录详情
1-6aa90e11-154daa-eeba87c429a8
success
2026-09-15 17:23:34
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解析时间
parsed_at
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文件类型
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姓名
name
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"name": "汪超",
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"education": [
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"major": "微电子科学与工程",
"degree": "本科",
"graduation_year": "2021\/06"
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"expected_salary": null,
"expected_city": null,
"availability": null
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"VHDL",
"C语言",
"Linux",
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"kintex7",
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"NORFlash",
"NANDFlash",
"SRAM",
"ROM",
"RAM",
"nvSRAM",
"PSRAM",
"Formality",
"XilinxArtixUltrascale+",
"pciexdma",
"lattice lifcl-40",
"mipi csi-2",
"isp",
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"Xilinx IP MIG",
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"company": "成都傅立叶电子科技有限公司",
"position": "FPGA开发工程师",
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"description": "一、6.4G采样率信号采集处理系统（周期5个月）：ZynqUltrascale+MPSOC PL端的设计，ADC12DJ3200和LMX04832芯片配置，jesd204b、DDR4集成和DMA PL端AXIS写端口设计。二、整网控守（周期3个月）：DMA PL端AXIS写数据端口调试。三、被动雷达信号采集和处理系统（周期4个月）：与同事联合调试板间数据传输。"
},
{
"company": "厦门码灵半导体技术有限公司",
"position": "数字IC设计工程师",
"duration": "2022\/05 - 2024\/05",
"description": "一、IP添加DMAC（周期3个月）：给一个IP添加DMAC，解决带宽不够的问题，验证环境是基于ARM的SOC系统。二、AudioIP的I2S和I2C接口模块集成及验证（周期3个月）：用APB接口的I2S和I2C IP连接AudioIP并验证AudioIP的I2S和I2C接口功能，验证环境是基于ARM的SOC系统。三、FSMC IP功能修改和验证（周期12个月）：FSMC(灵活静态存储控制器)IP关于PSRAM接口部分的设计，NORFlash、nvSRAM、PSRAM接口以及DMA的功能验证，验证环境是基于ARM的SOC系统。四、EtherCAT IP RTL HDL转换及形式验证（周期5个月）：将EtherCAT IP综合后看其面积，将EtherCAT IP的RTL从VHDL转换成Verilog并与原RTL进行形式验证。"
},
{
"company": "四川新盛唐谱锐光电科技有限公司",
"position": "FPGA开发工程师",
"duration": "2026\/04 - 2026\/09",
"description": "一、125MAD采集pcie传输（周期1个月）：adc采集传输给ArtixUltrascale+，缓存到ddr4，用pciexdma传输到pc。ad芯片控制，ad数据采集，并搬运到ddr4，ddr4和pcie IP移植。二、cmos图像处理ps显示（周期2个月）：cmos芯片采集图像raw数据，通过mipi csi-2接口传输到fpga，经过简单isp转成rgb888，通过千兆网上传给ps，ps经过处理，用窗口显示出图像。CMOS控制，mipi接口设计，isp模块设计，千兆网设计。"
}
],
"project_experience": [
{
"name": "6.4G采样率信号采集处理系统",
"role": "FPGA开发工程师",
"duration": "5个月",
"description": "ZynqUltrascale+MPSOC PL端的设计，ADC12DJ3200和LMX04832芯片配置，jesd204b、DDR4集成和DMA PL端AXIS写端口设计。"
},
{
"name": "整网控守",
"role": "FPGA开发工程师",
"duration": "3个月",
"description": "DMA PL端AXIS写数据端口调试。"
},
{
"name": "被动雷达信号采集和处理系统",
"role": "FPGA开发工程师",
"duration": "4个月",
"description": "与同事联合调试板间数据传输。"
},
{
"name": "IP添加DMAC",
"role": "数字IC设计工程师",
"duration": "3个月",
"description": "给一个IP添加DMAC，解决带宽不够的问题，验证环境是基于ARM的SOC系统。"
},
{
"name": "AudioIP的I2S和I2C接口模块集成及验证",
"role": "数字IC设计工程师",
"duration": "3个月",
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{
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"role": "数字IC设计工程师",
"duration": "12个月",
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},
{
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},
{
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},
{
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},
{
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"role": "自学",
"duration": "2025\/06",
"description": "用Xilinx IP MIG控制ddr2读写，并检测读出数据是否错误，MIG使用userinterface接口或axi4接口，结果读出数据没有错误。FPGA用的是xc7k70tfbg676-1，ddr2是三星的K4T1G164QG-BCE7，容量128MB，位宽16位，共两片，组成800Mhz数据传输速率，32位位宽，总容量256MB，行地址13位宽，列地址10位宽，bank地址3位宽。"
}
],
"certifications": [],
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创建时间
created_at
2026-09-15 17:23:34